Mouna Karmani

发表

A Fault -32 nm CMOS Double Sideband tolerant 32 nm CMOS Double Sideband tolerant 32 nm CMOS Double Sideband tolerant 32 nm CMOS Double Sideband

Chi-Un Lei, Mouna Karmani, Chiraz Khedhiri, 2012 .

AN EFFICIENT DIFFERENTIAL FULL ADDER

Ka Lok Man, Mouna Karmani, Chiraz Khedhiri, 2013 .

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, 2011, VLSIC 2011.

A Hardware-Software Codesign Case Study: The SHA3-512 algorithm Implementation on the LEON3 Processor

Mouna Karmani, Noura Benhadjyoussef, Belgacem Hamdi, 2020, 2020 5th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP).

A design for testability approach for nano-CMOS analogue integrated circuits

Rached Tourki, Ka Lok Man, Mouna Karmani, 2013 .

A CONCURRENT ERROR DETECTION AND CORRECTION BASED FAULT-TOLERANT XOR-XNOR CIRCUIT FOR HIGHLY RELIABLE APPLICATIONS

K. L. Man, Chi-Un Lei, Ka Lok Man, 2013 .

Design for testability in nano-CMOS analog integrated circuits using a new design analog checker

Ka Lok Man, Mouna Karmani, Chiraz Khedhiri, 2011, 2011 International SoC Design Conference.

Design of a Reliable XOR-XNOR Circuit for Arithmetic Logic Units

Amir-Mohammad Rahmani, Ka Lok Man, Kaiyu Wan, 2012, NPC.

A Fault-tolerant 32 nm CMOS Double Sideband Amplitude Suppressed Carrier Modulator-Demodulator Circuit Implementation

Cu Lei, Ka Lok Man, Mouna Karmani, 2012 .

A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

Mohsen Machhout, Mouna Karmani, Belgacem Hamdi, 2020, J. Circuits Syst. Comput..

A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

Chi-Un Lei, Ka Lok Man, Eng Gee Lim, 2012 .

Concurrent Error Detection Adder Based on Two Paths Output Computation

Ka Lok Man, Mouna Karmani, Chiraz Khedhiri, 2011, 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications Workshops.

ANALOG INTEGRATED CIRCUIT DESIGN AND TESTING USING THE FIELD PROGRAMMABLE ANALOG ARRAY TECHNOLOGY

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, 2011 .

Design and test challenges in Nano-scale analog and mixed CMOS technology

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, 2011 .

A B IST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, 2011 .

Power Analysis for Smartcard's Authentication-Protocol

Hassen Mestiri, Mouna Karmani, Noura Benhadjyoussef, 2019, 2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET).

A self-test and self-repair approach for analog integrated circuits

Amir-Mohammad Rahmani, Ka Lok Man, Tomas Krilavicius, 2012, 2012 2nd Baltic Congress on Future Internet Communications.

The Secured AES designs against Fault Injection Attacks: A comparative Study

Mouna Karmani, Noura Benhadjyoussef, Mohsen Machhout, 2020, 2020 5th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP).

A Fault Detection AES Scheme for Resource-Constrained Embedded Systems

Hassen Mestiri, Mouna Karmani, Noura Benhadjyoussef, 2019, 2019 International Conference on Advanced Systems and Emergent Technologies (IC_ASET).

A Self-checking CMOS Full adder in Double Pass Transistor Logic

Ka Lok Man, Mouna Karmani, Chiraz Khedhiri, 2012 .

Power-based Side Channel Analysis and Fault Injection: Hacking Techniques and Combined Countermeasure

Mohsen Machhout, Mouna Karmani, Noura Benhadjyoussef, 2021 .

The DFA/DFT-based hacking techniques and countermeasures: Case study of the 32-bit AES encryption crypto-core

Mohsen Machhout, Mouna Karmani, Belgacem Hamdi, 2021, IET Comput. Digit. Tech..

A Differential Double Pass Transistor Logic Unit

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, 2012 .