Scott C. Smith

发表

Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput

Scott C. Smith, S. Smith, 2004, ESA/VLSI.

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Jia Di, Scott C. Smith, Andrew Bailey, 2008, J. Low Power Electron..

Optimization of NULL convention self-timed circuits

Ronald F. DeMara, Scott C. Smith, Jiann S. Yuan, 2004, Integr..

Static implementation of quasi-delay-insensitive Pre-Charge Half-Buffers

Liang Zhou, Scott C. Smith, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits

Scott C. Smith, Sudarshan K. Srinivasan, Ashiq A. Sakib, 2018, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS).

CMOS Implementation of Threshold Gates with Hysteresis

Farhad Alibeygi Parsan, Scott C. Smith, F. A. Parsan, 2012, VLSI-SoC.

Design of a logic element for implementing an asynchronous FPGA

Scott C. Smith, S. Smith, 2007, FPGA '07.

Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation

Scott C. Smith, Anshul Singh, S. Smith, 2005, CDES.

Design and Characterization of NULL Convention Arithmetic Logic Units

Scott C. Smith, Satish K. Bandapati, S. Smith, 2007, VLSI.

Automated verification of input completeness for NCL circuits

Scott C. Smith, Sudarshan K. Srinivasan, S. Le, 2018 .

Abstraction techniques to improve scalability of equivalence verification for NCL circuits

Scott C. Smith, Vidura Wijayasekara, A. T. Rollie, 2016 .

Formal verification of NCL circuits

Scott C. Smith, Sudarshan K. Srinivasan, Ashiq A. Sakib, 2019 .

CMOS implementation of static threshold gates with hysteresis: A new approach

Farhad Alibeygi Parsan, Scott C. Smith, F. A. Parsan, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Integrating Asynchronous Paradigms into a VLSI Design Course

Waleed K. Al-Assadi, Scott C. Smith, S. Smith, 2009 .

Delay-insensitive gate-level pipelining

Ronald F. DeMara, Scott C. Smith, Jiann S. Yuan, 2001, Integr..

Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy

Scott C. Smith, S. Smith, 2003, VLSI.

Particle Swarm Optimization: A Hardware Implementation

Ganesh K. Venayagamoorthy, Scott C. Smith, Parviz Palangpour, 2009, CDES.

Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design

Scott C. Smith, Waleed Al-Assadi, Shabab F. Alam, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Design of a NULL Convention Self-Timed Divider

Scott C. Smith, S. Smith, 2004, ESA/VLSI.

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

Jia Di, Scott C. Smith, Chris Porter, 2013, Microelectron. J..

Speedup of self-timed digital systems using Early Completion

Scott C. Smith, S. Smith, 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Jia Di, Scott C. Smith, Ravi S. P. Nair, 2015 .

An Ancillary Services Model for Data Centers and Power Systems

Albert Y. Zomaya, Keqin Li, Samee U. Khan, 2020, IEEE Transactions on Cloud Computing.

High-Speed Energy Estimation for Delay-Insensitive Circuits

Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith, 2005, CDES.

Gate and throughput optimizations for null convention self-timed digital circuits

Ronald F. DeMara, Scott C. Smith, R. Demara, 2001 .

A differential design for C-elements and NCL gates

Scott C. Smith, Steven Yancey, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Asynchronous Digital Circuits

Jia Di, Scott C. Smith, 2012 .

Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

Waleed K. Al-Assadi, Farhad Alibeygi Parsan, Scott C. Smith, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An FPGA-in-the-loop approach for HDL motor controller verification

Paul Rogers, Scott C. Smith, Rajesh Kavasseri, 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Automated energy calculation and estimation for delay-insensitive digital circuits

Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith, 2007, Microelectron. J..

NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation

Ronald F. DeMara, Scott C. Smith, Jiann S. Yuan, 2002, J. Syst. Archit..

Integrated software-hardware design for ultra-low power infrastructure monitoring

Jingxian Wu, Scott C. Smith, 2009, 2009 12th International IEEE Conference on Intelligent Transportation Systems.

Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Jia Di, Scott C. Smith, 2009, Designing Asynchronous Circuits using NULL Convention Logic.

A robust, wide-temperature data transmission system for space environments

Jim Holmes, Scott C. Smith, H. Alan Mantooth, 2013, 2013 IEEE Aerospace Conference.

Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

Liang Zhou, Jia Di, Scott C. Smith, 2015 .

Sleep Convention Logic using partially slept function blocks

Scott C. Smith, Parviz Palangpour, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits

Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav Singhal, 2007, Eng. Appl. Artif. Intell..

Formal Modeling and Verification of PCHB Asynchronous Circuits

Scott C. Smith, Sudarshan K. Srinivasan, Ashiq A. Sakib, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implementation of Design For Test for Asynchronous NCL Designs

Waleed K. Al-Assadi, Bonita Bhaskaran, Venkat Satagopan, 2005, CDES.

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs

Tao Zhang, Yuan Xie, Jia Di, 2009, 2009 IEEE International Conference on 3D System Integration.

Group Selection in a Senior/Graduate Level Digital Circuit Design Course

Scott C. Smith, 2005 .

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

Scott C. Smith, Sudarshan K. Srinivasan, Ashiq A. Sakib, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology

Liang Zhou, Jia Di, Scott C. Smith, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Design and characterization of null convention self-timed multipliers

Minsu Choi, Scott C. Smith, Satish K. Bandapati, 2003, IEEE Design & Test of Computers.

Delay-Insensitive Ternary Logic

Jia Di, Scott C. Smith, Ravi Sankar Parameswaran Nair, 2009, CDES.

Analysis and design of CMOS resettable C-elements

Scott C. Smith, Nasim Soufizadeh-Balaneji, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

MTD 3 L: a secure IC design methodology with reduced overhead

Jia Di, Scott C. Smith, Michael Linder, 2012 .

Equivalence verification for NULL Convention Logic (NCL) circuits

Scott C. Smith, Sudarshan K. Srinivasan, Vidura Wijayasekara, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits

Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith, 2005 .

Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology

Jia Di, Scott C. Smith, Michael Linder, 2013 .

Performance optimization of rotation-tolerant Viola–Jones-based blackbird detection

Scott C. Smith, Roger Green, Nauman Jalil, 2018, Journal of Real-Time Image Processing.

Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits

Waleed K. Al-Assadi, Bonita Bhaskaran, Venkat Satagopan, 2007 .

Uncle - An RTL Approach to Asynchronous Design

Mitchell A. Thornton, Scott C. Smith, Robert B. Reese, 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

Design for Testability of Sleep Convention Logic

Waleed K. Al-Assadi, Farhad Alibeygi Parsan, Scott C. Smith, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors

Paul Rogers, Scott C. Smith, Rajesh Kavasseri, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation

Na Gong, Hritom Das, Scott C. Smith, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.