Bogdan F. Romanescu

Specifying and dynamically verifying address translation-aware memory consistency

Daniel J. Sorin, Bogdan F. Romanescu, Alvin R. Lebeck, 2010, ASPLOS 2010.

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching

Sule Ozev, Daniel J. Sorin, Bogdan F. Romanescu, 2008, CF '08.

UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all

Daniel J. Sorin, Bogdan F. Romanescu, Alvin R. Lebeck, 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

Address Translation Aware Memory Consistency

Daniel J. Sorin, Bogdan F. Romanescu, Alvin R. Lebeck, 2011, IEEE Micro.

Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors

Bogdan F. Romanescu, 2010 .

Core Cannibalization Architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults

Daniel J. Sorin, Bogdan F. Romanescu, 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

Specifying and dynamically verifying address translation-aware memory consistency

Daniel J. Sorin, Bogdan F. Romanescu, Alvin R. Lebeck, 2010, ASPLOS XV.

Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation

Sule Ozev, Daniel J. Sorin, Bogdan F. Romanescu, 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

VariaSim: simulating circuits and systems in the presence of process variability

Sule Ozev, Daniel J. Sorin, Bogdan F. Romanescu, 2007, CARN.

Quantifying the Impact of Process Variability on Microprocessor Behavior

Sule Ozev, Daniel J. Sorin, Bogdan F. Romanescu, 2006 .

A Case for Computer Architecture Performance Metrics that Reflect Process Variability

Sule Ozev, Daniel J. Sorin, Bogdan F. Romanescu, 2007 .