Jyi-Tsong Lin

发表

A new type of CMOS inverter with Lubistor load and NMOS driver

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, 2010, 2010 International Symposium on Next Generation Electronics.

Unipolar CMOS inverter based on punch-through effect with two embedded oxide structure

Jyi-Tsong Lin, Hsuan-Hsu Chen, Chia-Hsien Lin, 2011, 2011 IEEE International Conference of Electron Devices and Solid-State Circuits.

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2013, IEEE Transactions on Electron Devices.

Characterisation of new vertical MOSFETs with recessed gate

Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hao Kuo, 2010, 2010 International Symposium on Next Generation Electronics.

A novel finfet-based 1T-dram with extended body using gate-induced drain leakage mechanism

Jyi-Tsong Lin, Cheng-Hsien Chang, Po-Hsieh Lin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FET

Jyi-Tsong Lin, Yi-Chuen Eng, 2008, J. Comput..

A new low power unipolar CMOS

Yong-Huang Lin, Jyi-Tsong Lin, Steve Haga, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Performance Assessment of TFET Architectures as 1T-DRAM

Abhinav Kranti, Jyi-Tsong Lin, Nupur Navlakha, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Twin gate Tunnel FET based capacitorless dynamic memory

Abhinav Kranti, Jyi-Tsong Lin, Nupur Navlakha, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Self-Aligned SOl MOSFETswith !!-Shaped Conductive Layer and SourcelDrain-Tie

Jyi-Tsong Lin, Hsuan-Hsu Chen, Chih-Hao Kuo, 2009 .

A new approach to wafer sawing: stealth laser dicing technology

Jyi-Tsong Lin, Yen-Chi Lee, 2015, 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Design optimization of tunnel FET for dynamic memory applications

Abhinav Kranti, Jyi-Tsong Lin, Nupur Navlakha, 2017, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Optimization of back gate workfunction, alignment and bias for charge retention in TFET based DRAM

Abhinav Kranti, Jyi-Tsong Lin, Nupur Navlakha, 2016, 2016 3rd International Conference on Emerging Electronics (ICEE).

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors

Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang, 2017, Microelectron. Reliab..

A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage

Abhinav Kranti, Jyi-Tsong Lin, Wei-Han Lee, 2017, IEEE Journal of the Electron Devices Society.

Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory

Abhinav Kranti, Jyi-Tsong Lin, Nupur Navlakha, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Novel 1T-dram with fin-gate and pillar structure for hole storage and data retention time improvement

Yong-Huang Lin, Jyi-Tsong Lin, Po-Hsieh Lin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Punch-through reading mechanism and body raised up structure for a novel Punch-Through DRAM

Abhinav Kranti, Jyi-Tsong Lin, Wei-Han Lee, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A novel dual-channel body-tied MOSFET with self-aligned structure for analog/RF applications

Jyi-Tsong Lin, Kuan-Yu Lu, Cheng-Hsin Chen, 2010, 2010 International Symposium on Next Generation Electronics.

A novel non-classical unipolar CMOS inverter with elevated body and two embedded oxide

Yong-Huang Lin, Jyi-Tsong Lin, Po-Hsieh Lin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A Kink-Free Bottom Gate Poly-Si Thin-Film Transistor with Smart Body Tie

Jyi-Tsong Lin, Kuo Dong Huang, Shih-Tsong Lin, 2007 .

Design theory and fabrication process of 90nm unipolar-CMOS

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, 2010, 2010 Silicon Nanoelectronics Workshop.

Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure

Yu-Chun Wang, Yong-Huang Lin, Jyi-Tsong Lin, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Source/drain-tied bottom gate MOSFET for device reliability improvement

Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, 2008, 2008 26th International Conference on Microelectronics.

A high performance junctionless PTGVMOS with native tie for deca- nanometer regime

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI

Jyi-Tsong Lin, Yi-Chuen Eng, Kao-Cheng Lin, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A new type of CMOS inverter with Lubistor load and TFET driver for sub-20 nm technology generation

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

An improved unipolar CMOS with elevated body and spacer for low-power application

Yong-Huang Lin, Jyi-Tsong Lin, Wei-Han Lee, 2015, 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

A unipolar-CMOS with recessed source/drain load

Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, 2011, 2011 9th IEEE International Conference on ASIC.

A new 1T DRAM cell with enhanced floating body effect

Jyi-Tsong Lin, Mike Chang, 2006, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06).

An initial overdriven sense amplifier for low voltage DRAMs

Jyi-Tsong Lin, Cheng-Chih Hsu, Jyi-Tsong Lin, 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).

A novel self-align double gate MOSFET with source/drain tie

Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Impact ofSource/Drain Tieona30nmBottomGate MOSFETs

Jyi-Tsong Lin, Jeng-Da Lin, Kung-Kai Kao, 2007 .

A Steep Subthreshold Swing Technique for Gate-All-Around SOI MOSFETs

Jyi-Tsong Lin, Meng-Hsueh Chiang, Wei-Chou Hsu, 2015 .

A novel low bias and high speed non-classical CMOS inverter with unique shared contact

Jyi-Tsong Lin, Wei-Han Lee, Kai-Cheng Juang, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Simulation study of a new capacitor-less DRAM with Vertical Nanometer Pillar

Yong-Huang Lin, Jyi-Tsong Lin, Po-Hsieh Lin, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Vertical Channel Capacitor-less One-Transistor DRAMs with a pass-way Trench for improving Retention Time

Abhinav Kranti, Jyi-Tsong Lin, Po-Hsieh Lin, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

Cheng-Hsin Chen, Jyi-Tsong Lin, Hsuan-Hsu Chen, 2010 .

Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

Jyi-Tsong Lin, Hsuan-Hsu Chen, Cheng-Hsin Chen, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Characteristics of Recessed-Gate TFETs With Line Tunneling

Jyi-Tsong Lin, Chih-Ting Yeh, Qing-Tai Zhao, 2018, IEEE Transactions on Electron Devices.

A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2010, 2010 International Symposium on Next Generation Electronics.

High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Jyi-Tsong Lin, Meng-Hsueh Chiang, Keunwoo Kim, 2010, 2010 IEEE International SOI Conference (SOI).

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

Jyi-Tsong Lin, Yi-Chuen Eng, 2007, IEEE Transactions on Electron Devices.

Multifunction Behavior of a Vertical MOSFET With Trench Body Structure and New Erase Mechanism for Use in 1T-DRAM

Jyi-Tsong Lin, Po-Hsieh Lin, 2014, IEEE Transactions on Electron Devices.

A compensation threshold voltage shift pixel circuit for active matrix organic light emitting diode

Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Neng Wen, 2008, 2008 26th International Conference on Microelectronics.

Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Thermal Stability of a Vertical SOI-Based Capacitorless One-Transistor DRAM with Trench-Body Structure

Jyi-Tsong Lin, Po-Hsieh Lin, 2013 .

A new process for self-aligned silicon-on-insulator with block oxide and its memory application for 1T-DRAM

Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.