L. Baud

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

B. Szelag, V. Knopik, P. Garcia, 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.

A multiple–shape channel selection filter for multimode zero–IF receiver using capacitor over active device implementation

D. Belot, A. Cathelin, L. Baud, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

O. Faynot, G. Ghibaudo, T. Ernst, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

O. Faynot, P. Batude, M. Vinet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain

M. Vinet, D. Lafond, S. Deleonibus, 2009, IEEE Electron Device Letters.

15nm-diameter 3D Stacked Nanowires with optional Independent Gates operation (?FET)

O. Faynot, Christian Arvet, S. Deleonibus, 2008 .

A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

Nicolas Loubet, Romain Wacquez, M.-P. Samson, 2007 .

High temperature silicon carbide MOSFETs with very low drain leakage current

P. Morfouli, L. Baud, Thierry Ouisse, 1994 .

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.