Satoshi Komatsu

发表

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2013, ISPD '13.

AMS Extensions for Timed/Untimed System-Level Design Language

Masahiro Fujita, Yu Liu, Satoshi Komatsu, 2005, FDL.

Field modifiable architecture with FPGAs and its design methodology

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures

Masahiro Fujita, Shanghua Gao, Satoshi Komatsu, 2007, IESS.

Synchronization verification in system-level design with ILP solvers

Masahiro Fujita, Satoshi Komatsu, Thanyapat Sakunkonchak, 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme

Masahiro Fujita, Satoshi Komatsu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Formal verification of hardware/software co‐designs with translation into representation by state transitions

Masahiro Fujita, Satoshi Komatsu, Takeshi Matsumoto, 2007 .

Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links

Kwang-Ting Cheng, Kunihiro Asada, Satoshi Komatsu, 2009, 2009 14th IEEE European Test Symposium.

A Framework on Synchronization Verification in System-Level Design

Masahiro Fujita, Satoshi Komatsu, Thanyapat Sakunkonchak, 2005 .

A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Field modifiable architecture with FPGAs and its design/verification/debugging methodologies

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, 2003, 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the.

Power integrity control of ATE for emulating power supply fluctuations on customer environment

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2012, 2012 IEEE International Test Conference.

FEM simulation of cracking in double shell tunnel lining system and investigation of crack mitigation techniques

Akira Hosoda, Satoshi Komatsu, Chamila K. Rankoth, 2016 .

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2016, IEICE Trans. Electron..

AnOptimization ofBusInterconnects Pitch for Low-power andReliable BusEncoding Scheme

Masahiro Fujita, Satoshi Komatsu, 2006 .

Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment

Masahiro Fujita, Yu Liu, Satoshi Komatsu, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An equivalent-time and clocked approach for continuous-time quantization

Kunihiro Asada, Takahiro J. Yamaguchi, Takafumi Aoki, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures

Masahiro Fujita, Hiroaki Yoshida, Shanghua Gao, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links

Kwang-Ting Cheng, Kunihiro Asada, Satoshi Komatsu, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A New Procedure for Measuring High-Accuracy Probability Density Functions

Kunihiro Asada, Takahiro J. Yamaguchi, Kiichi Niitsu, 2012, 2012 IEEE 21st Asian Test Symposium.

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction

Masahiro Fujita, Satoshi Komatsu, Thanyapat Sakunkonchak, 2007, ATVA.

Targeting Leakage Constraints during ATPG

Masahiro Fujita, Görschwin Fey, Satoshi Komatsu, 2008, 2008 17th Asian Test Symposium.

Efficient Test Generation Framework for Analog LSI with Behavior Model : (Invited Paper)

Satoshi Komatsu, Yuichi Miyazawa, 2018, 2018 International Conference on Advanced Technologies for Communications (ATC).

A novel test structure for measuring the threshold voltage variance in MOSFETs

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2013, 2013 IEEE International Test Conference (ITC).

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

The AMS Extension to System Level Design Language - SpecC

Masahiro Fujita, Yu Liu, Satoshi Komatsu, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm

Masahiko Yoshimoto, Mikio Yagi, Masayuki Miyama, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

Irredundant address bus encoding techniques based on adaptive codebooks for low power

Masahiro Fujita, Satoshi Komatsu, 2003, ASP-DAC '03.

Clocked comparator for high-speed applications in 65nm technology

Kunihiro Asada, Satoshi Komatsu, Mohamed Abbas, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Signature-based testing for adaptive digitally-calibrated pipelined analog-to-digital converters

Kunihiro Asada, Satoshi Komatsu, Mohamed Abbas, 2009, 2009 IEEE 8th International Conference on ASIC.

An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video

Masahiko Yoshimoto, Junichi Miyakoshi, Mikio Yagi, 2003 .

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, 2002, International Workshop on Logic & Synthesis.

Characteristics optimization of stochastic ADC and its automatic generation system

Satoshi Komatsu, Ryosuke Yumoto, S. Komatsu, 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

Equivalence checking in C-based system-level design by sequentializing concurrent behaviors

Takeshi Matsumoto, Masahiro Fujita, Satoshi Komatsu, 2007 .

Comparative study on verilog-based and C-based hardware design education

Masahiro Fujita, Makoto Ikeda, Kunihiro Asada, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Low power microprocessors for comparative study on bus architecture and multiplexer architecture

Makoto Ikeda, Kunihiro Asada, Satoshi Komatsu, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2014, 2014 IEEE 23rd Asian Test Symposium.

Dynamically reconfigurable protocol transducer

Masahiro Fujita, Satoshi Komatsu, Kenshu Seto, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Approaches for Reducing Power Consumption in VLSI Bus Circuits

Kunihiro Asada, Makoto Ikeda, Satoshi Komatsu, 2000 .

Practical proof of CP element based design for 14nm node and beyond

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2013, Advanced Lithography.

System level design language extensions for timed/untimed digital-analog combined system design

Masahiro Fujita, Yu Liu, Satoshi Komatsu, 2005, GLSVLSI '05.

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2016, J. Electron. Test..

SAT-based ATPG testing of inter- and intra-gate bridging faults

Makoto Ikeda, Kunihiro Asada, Satoshi Komatsu, 2009, 2009 European Conference on Circuit Theory and Design.

CP element based design for 14nm node EBDW high volume manufacturing

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2012, Advanced Lithography.

A stochastic sampling time-to-digital converter with tunable 180–770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications

Masahiro Fujita, Satoshi Komatsu, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Protocol Transducer Synthesis using Divide and Conquer approach

Masahiro Fujita, Shigeru Watanabe, Satoshi Komatsu, 2007, 2007 Asia and South Pacific Design Automation Conference.

Pipeline scheduling for array based reconfigurable architectures considering interconnect delays

Masahiro Fujita, Shanghua Gao, Satoshi Komatsu, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Engineering changes in field modifiable architectures

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

Synchronization verification in system-level design with ILP solvers

Masahiro Fujita, Satoshi Komatsu, Thanyapat Sakunkonchak, 2005 .

An SoC platform with on-chip web interface for in-field monitoring

Tetsuya Iizuka, Kunihiro Asada, Hiroaki Yoshida, 2009, 2009 International SoC Design Conference (ISOCC).

Low power chip interface based on bus data encoding with adaptive code-book method

Makoto Ikeda, Kunihiro Asada, Satoshi Komatsu, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters

Kunihiro Asada, Takahiro J. Yamaguchi, Satoshi Komatsu, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

A low — Voltage hysteresis comparator for low power applications

Satoshi Komatsu, Takumi Saito, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing

Makoto Ikeda, Tetsuya Iizuka, Kunihiro Asada, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Practical Course of Design, Fabrication and Testing of CMOS Gate Array

Minoru Fujishima, Makoto Ikeda, Kunihiro Asada, 2004 .

VLSI Test Exercise Courses for Students in EE Department

Satoshi Komatsu, 2008, 2008 IEEE International Test Conference.

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2014, 2014 International Test Conference.

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks

Masahiro Fujita, Satoshi Komatsu, 2003 .

Application of a continuous-time level crossing quantization method for timing noise measurements

Kunihiro Asada, Takahiro J. Yamaguchi, Takafumi Aoki, 2011, 2011 IEEE International Test Conference.

A Framework for Automatic Generation of Fully Synthesizable ADPLL

Satoshi Komatsu, Shinya Ubukata, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Adaptive codebook encoding for low‐power chip interface

Kunihiro Asada, Makoto Ikeda, Satoshi Komatsu, 2000 .