M. Niewczas

Hierarchical circuit comparison as a top-down VLSI design verification technique

M. Niewczas, K. Woźniakowski, 1993 .

Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

Zbigniew Jaworski, E. Piwowarska, A. Wojtasik, 1993 .

Characterisation of the threshold voltage variation: a test chip and the results

M. Niewczas, 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

Application of the recognition technique to bottom-up VLSI design verification

W. Kuźmicz, M. Niewczas, C. Lichacz, 1993 .

Chip scale 3-D topography synthesis

Andrzej J. Strojwas, Wojciech Maly, M. Niewczas, 1998 .

Resistive Plate Chamber (RPC) based Muon Trigger System for the CMS experiment – PAttern Comparator ASIC

Wieslaw Kuzmicz, Zbigniew Jaworski, I. M. Kudla, 1998 .