Franck Dosseul

DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION

G. Parès, A. Attard, Franck Dosseul, 2013 .

3D finite element modeling of 3D C2W (chip to wafer) drop test reliability: Optimization of internal architecture and materials

Abdelhake Bouchou, Franck Dosseul, Soufyane Belhenini, 2014, Microelectron. Reliab..

Outperformance of Cu pillar flip chip bumps in electromigration testing

Bart Vandevelde, Eric Beyne, Riet Labie, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Electromigration failure mechanisms for different flip chip bump configurations

Bart Vandevelde, Riet Labie, Kristof Croes, 2011, 2011 International Reliability Physics Symposium.