Pranav Ashar

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Synthesis techniques for low-power digital designs

Miodrag Potkonjak, Sujit Dey, Pranav Ashar, 1995 .

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Test generation for cyclic combinational circuits

Sharad Malik, Anand Raghunathan, Pranav Ashar, 1995, Proceedings of the 8th International Conference on VLSI Design.

Panel: Assertion-Based Verification -What's the Big Deal?

Alan J. Hu, Sandeep K. Shukla, Avner Landver, 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

Encoding of Symbolic Outputs

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

Path-delay-fault testability properties of multiplexor-based networks

Kurt Keutzer, Srinivas Devadas, Pranav Ashar, 1993, Integr..

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Sharad Malik, Aarti Gupta, Malay K. Ganai, 2002, DAC '02.

Efficient distributed SAT and SAT-based distributed Bounded Model Checking

Zijiang Yang, Aarti Gupta, Malay K. Ganai, 2005, International Journal on Software Tools for Technology Transfer.

Verification of RTL generated from scheduled behavior in a high-level synthesis flow

Anand Raghunathan, Subhrajit Bhattacharya, Pranav Ashar, 1998, ICCAD.

Failures and verification solutions related to untimed paths in SOCs

Vinod Viswanath, Pranav Ashar, Vikas Sachdeva, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications

Sharad Malik, Pranav Ashar, 1994, 31st Design Automation Conference.

Solving Boolean Satisfiability with Dynamic Hardware Configurations

Sharad Malik, Margaret Martonosi, Pranav Ashar, 1998, FPL.

An edge-endpoint-based configurable hardware architecture for VLSI CAD layout design rule checking

Margaret Martonosi, Zhen Luo, Pranav Ashar, 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

Iterative Abstraction using SAT-based BMC with Proof Analysis

Zijiang Yang, Aarti Gupta, Pranav Ashar, 2003, ICCAD 2003.

Verification of a combinational loop based arbitration scheme in a system-on-chip integration architecture

Yang Xia, Pranav Ashar, P. Ashar, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Using Complete-1-Distinguishability for FSM equivalence checking

Sharad Malik, Aarti Gupta, Pranav Ashar, 1996, Proceedings of International Conference on Computer Aided Design.

Fast functional simulation using branching programs

Sharad Malik, Pranav Ashar, 1995, ICCAD.

Guarded evaluation: pushing power management to logic synthesis/design

Sharad Malik, Vivek Tiwari, Pranav Ashar, 1995, ISLPED '95.

Using complete-1-distinguishability for FSM equivalence checking

Sharad Malik, Aarti Gupta, Pranav Ashar, 1996, ICCAD.

Clock domain verification challenges and scalable solutions

Pranav Ashar, 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Efficient Breadth-first Manipulation Of Binary Decision Diagrams

Pranav Ashar, Matthew Cheong, P. Ashar, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Gate-delay-fault testability properties of multiplexor-based networks

Kurt Keutzer, Srinivas Devadas, Pranav Ashar, 1991, 1991, Proceedings. International Test Conference.

Multiple fault testable sequential circuits

Srinivas Devadas, Pranav Ashar, A. R. Newton, 1990, IEEE International Symposium on Circuits and Systems.

Efficient Modeling of Embedded Memories in Bounded Model Checking

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2004, CAV.

Efficient distributed SAT and SAT-based distributed Bounded Model Checking

Zijiang Yang, Aarti Gupta, Malay K. Ganai, 2003, International Journal on Software Tools for Technology Transfer.

Conclusions and Directions for Future Work

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

Gate-delay-fault testability properties of multiplexor-based networks

Kurt Keutzer, Srinivas Devadas, Pranav Ashar, 1993, Formal Methods Syst. Des..

Irredundant interacting sequential machines via optimal logic synthesis

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testability properties of multilevel logic networks derived from binary decision diagrams

Kurt Keutzer, Srinivas Devadas, Pranav Ashar, 1991 .

F-Soft: Software Verification Platform

Zijiang Yang, Aarti Gupta, Malay K. Ganai, 2005, CAV.

Dynamic detection and removal of inactive clauses in SAT with application in image computation

Zijiang Yang, Aarti Gupta, Pranav Ashar, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Optimum and heuristic algorithms for an approach to finite state machine decomposition

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Verification of embedded memory systems using efficient memory modeling

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2005, Design, Automation and Test in Europe.

SAT-Based Image Computation with Application in Reachability Analysis

Zijiang Yang, Aarti Gupta, Pranav Ashar, 2000, FMCAD.

Basic Definitions and Concepts

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

Accelerating Boolean satisfiability with configurable hardware

Sharad Malik, Margaret Martonosi, Pranav Ashar, 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

Using configurable computing to accelerate Boolean satisfiability

Sharad Malik, Margaret Martonosi, Pranav Ashar, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A unified approach to the decomposition and re-decomposition of sequential machines

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1991, DAC '90.

Exploiting multi-cycle false paths in the performance optimization of sequential circuits

Sharad Malik, Sujit Dey, Pranav Ashar, 1992, ICCAD.

Functional timing analysis using ATPG

Sharad Malik, Pranav Ashar, S. Rothweiler, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

Sequential Don’t Cares

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

Exploiting Retiming in a Guided Simulation Based Validation Methodology

Sharad Malik, Aarti Gupta, Pranav Ashar, 1999, CHARME.

Simulation vector generation from HDL descriptions for observability-enhanced statement coverage

Srinivas Devadas, Farzan Fallah, Pranav Ashar, 1999, DAC '99.

Boolean satisfiability and equivalence checking using general binary decision diagrams

Srinivas Devadas, Abhijit Ghosh, Pranav Ashar, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Test generation for cyclic combinational circuits

Sharad Malik, Anand Raghunathan, Pranav Ashar, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Iterative Abstraction using SAT-based BMC with Proof Analysis

Zijiang Yang, Aarti Gupta, Malay K. Ganai, 2003, ICCAD.

Closing the Verification Gap with Static Sign-off

Vinod Viswanath, Pranav Ashar, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Efficient SAT-based bounded model checking for software verification

Malay K. Ganai, Aarti Gupta, Pranav Ashar, 2008, Theor. Comput. Sci..

Static verification based signoff - A key enabler for managing verification complexity in the modern soc

Pranav Ashar, 2013, 2013 Formal Methods in Computer-Aided Design.

Implicit state transition graphs: applications to sequential logic synthesis and test

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

A paradigm shift in verification methodology

Pranav Ashar, 2016, 2016 Formal Methods in Computer-Aided Design (FMCAD).

Encoding of Symbolic Inputs

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

Fast functional simulation using branching programs

Sharad Malik, Pranav Ashar, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Technology Mapping for Low Power

Sharad Malik, Vivek Tiwari, Pranav Ashar, 1993, 30th ACM/IEEE Design Automation Conference.

Toward formalizing a validation methodology using simulation coverage

Sharad Malik, Aarti Gupta, Pranav Ashar, 1997, DAC.

Functional vector generation for sequential HDL models under an observability-based code coverage metric

Srinivas Devadas, Farzan Fallah, Pranav Ashar, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Abstraction and BDDs Complement SAT-Based BMC in DiVer

Chao Wang, Zijiang Yang, Aarti Gupta, 2003, CAV.

Technology mapping for low power in logic synthesis

Sharad Malik, Vivek Tiwari, Pranav Ashar, 1996, Integr..

Integrating a Boolean satisfiability checker and BDDs for combinational equivalence checking

Aarti Gupta, Pranav Ashar, Aarti Gupta, 1998, Proceedings Eleventh International Conference on VLSI Design.

Lazy constraints and SAT heuristics for proof-based abstraction

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability

Sharad Malik, Margaret Martonosi, Pranav Ashar, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Property-specific witness graph generation for guided simulation

Kazutoshi Wakabayashi, S. Liu, Aarti Gupta, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Anand Raghunathan, Subhrajit Bhattacharya, Aarti Gupta, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Scheduling techniques to enable power management

José C. Monteiro, Srinivas Devadas, Pranav Ashar, 1996, DAC '96.

Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking

Srihari Cadambi, Zijiang Yang, Aarti Gupta, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking

Margaret Martonosi, Zhen Luo, Pranav Ashar, 2000, VLSI Design.

Learning from BDDs in SAT-based bounded model checking

Chao Wang, Zijiang Yang, Aarti Gupta, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Exploiting multicycle false paths in the performance optimization of sequential logic circuits

Sharad Malik, Sujit Dey, Pranav Ashar, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Using range analysis for software verification

Anoop Gupta, Srihari Cadambi, Zijiang Yang, 2006 .

Efficient breadth-first manipulation of binary decision diagrams

Pranav Ashar, Matthew Cheong, 1994, ICCAD.

Property-specific testbench generation for guided simulation

Kazutoshi Wakabayashi, Aarti Gupta, Albert E. Casavant, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2005, TACAS.

Guarded evaluation: pushing power management to logic synthesis/design

Sharad Malik, Vivek Tiwari, Pranav Ashar, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Finite State Machine Decomposition

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1992 .

A fast, inexpensive and scalable hardware acceleration technique for functional simulation

Srihari Cadambi, Pranav Ashar, Chandra Mulpuri, 2002, DAC '02.

Testability driven synthesis of interacting finite state machines

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams

Srinivas Devadas, Abhijit Ghosh, Pranav Ashar, 1992, Integr..

Partition-based decision heuristics for image computation using SAT and BDDs

Sharad Malik, Zijiang Yang, Aarti Gupta, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Optimum and heuristic algorithms for finite state machine decomposition and partitioning

Srinivas Devadas, A. Richard Newton, Pranav Ashar, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Beyond safety: customized SAT-based model checking

Aarti Gupta, Malay K. Ganai, Pranav Ashar, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Functional timing analysis using ATPG

Sharad Malik, Pranav Ashar, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Range analysis for software veriTcation

Malay K. Ganai, Pranav Ashar, Ilya Shlyakhter, 2005 .

Solving Boolean Satissability with Dynamic Hardware Conngurations

Sharad Malik, Margaret Martonosi, Pranav Ashar, 1998 .