B. Khan

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

K. McStay, G. Freeman, R. Krishnan, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

T. Kirihata, A. Blauberg, S. Narasimha, 2010, 2010 International Electron Devices Meeting.

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

B.J. Park, D. Shum, J. Liu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 0.168/spl mu/m/sup 2//0.11/spl mu/m/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

T. Kirihata, S.S. Iyer, J. Liu, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..