Philip H. Sweany

发表

Tiny split data-caches make big performance impact for embedded applications

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, J. Embed. Comput..

Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies

Philip H. Sweany, Steve Carr, Brett L. Huber, 1998, Digit. Tech. J..

Trace scheduling optimization in a retargetable microcode compiler

Philip H. Sweany, Michael A. Howland, Robert A. Mueller, 1987, MICRO 20.

Optimizing loop performance for clustered VLIW architectures

Philip H. Sweany, Yi Qian, Steve Carr, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

Automatic Code Generation Through Model-Driven Design

Philip H. Sweany, Patrick W. Burke, P. Sweany, 2007 .

New Faculty Orientation And Seminar Series: Emphasis On Teaching And Learning

Philip H. Sweany, William W. Predebon, Peck Cho, 1996 .

Horizon: A Retargetable Compiler for Horizontal Microarchitectures

Philip H. Sweany, Robert A. Mueller, Michael R. Duda, 1988, IEEE Trans. Software Eng..

Loop Transformations for Architectures with Partitioned Register Banks

Philip H. Sweany, Steve Carr, Xianglong Huang, 2001, OM '01.

Improving software pipelining with unroll-and-jam

Philip H. Sweany, Chen Ding, Steve Carr, 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.

Register assignment for software pipelining with partitioned register banks

Philip H. Sweany, Steve Carr, Jason Hiser, 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.

Loop fusion for clustered VLIW architectures

Philip H. Sweany, Yi Qian, Steve Carr, 2002, LCTES/SCOPES '02.

An experimental evaluation of scalar replacement on scientific benchmarks

Philip H. Sweany, Steve Carr, S. Carr, 2003, Softw. Pract. Exp..

CRAIG: a practical framework for combining instruction scheduling and register assignment

Philip H. Sweany, Steve Carr, Thomas S. Brasier, 1995, PACT.

Value cloning for architectures with partitioned register banks

Philip H. Sweany, Steve Carr, Darla K. Kuras, 1998 .

An FPGA implementation of elliptic curve cryptography for future secure web transaction

Jian Huang, Philip H. Sweany, Hao Li, 2007, PDCS.

Debugging teacher certification (abstract only)

Jian Zhang, Philip H. Sweany, 2014, SIGCSE '14.

Speculative Thread Execution in a Multithreaded Dataflow Architecture

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, PDCS.

Using Genetic Algorithms to Fine-Tune Instruction-Scheduling Heuristics

Philip H. Sweany, Steven J. Beaty, Scott Colcord, 1999 .

Feasibility of decoupling memory management from the execution pipeline

Afrin Naz, Krishna M. Kavi, Wentong Li, 2007, J. Syst. Archit..

A Study of Separate Array and Scalar Caches

Afrin Naz, Krishna M. Kavi, Philip H. Sweany, 2004, HPCS.

Instruction Scheduling Using Simulated Annealing

Philip H. Sweany, Steven J. Beaty, 1998 .

Dominator-path scheduling: a global scheduling method

Philip H. Sweany, Steven J. Beaty, 1992, MICRO.

A Study of Reconfigurable Split Data Caches and Instruction Caches

Afrin Naz, Krishna M. Kavi, Wentong Li, 2006, PDCS.

Dominator-path scheduling: a global scheduling method

Philip H. Sweany, Steven J. Beaty, 1992, MICRO 1992.

Modulo Scheduling with Cache Reuse Information

Philip H. Sweany, Chen Ding, Steve Carr, 1997, Euro-Par.

Improving software pipelining with hardware support for self-spatial loads

Philip H. Sweany, Steve Carr, S. Carr, 1999, CARN.

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

Afrin Naz, Krishna M. Kavi, Philip H. Sweany, 2005, SIGARCH Comput. Archit. News.

Global register partitioning

Philip H. Sweany, Steve Carr, Jason Hiser, 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field

Jian Huang, Philip H. Sweany, Dijiang Huang, 2008, J. Syst. Archit..

Extending list scheduling to consider execution frequency

Philip H. Sweany, Steven J. Beaty, Michael J. Bourke, 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.

A Code Generation Framework for VLIW Architectures with Partitioned Register Banks

Philip H. Sweany, Steve Carr, Darla K. Kuras, 2007 .

Designing a pre-service CS teacher education program with a focus on diversity

Philip H. Sweany, 2015 .

Automatic data partitioning for the agere payload plus network processor

Philip H. Sweany, Steve Carr, 2004, CASES '04.

Building a retargetable local instruction scheduler

Philip H. Sweany, Bogong Su, Vicki H. Allan, 1998 .

Building a retargetable local instruction scheduler

Philip H. Sweany, Bogong Su, Vicki H. Allan, 1998, Softw. Pract. Exp..

Post-compaction register assignment in a retargetable compiler

Philip H. Sweany, Steven J. Beaty, S. Beaty, 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.

Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches

Philip H. Sweany, Steve Carr, Soner Onder, 2001 .

Post-compaction register assignment in a retargetable compiler

Philip H. Sweany, Steven J. Beaty, 1990, MICRO.

Inter-block code motion without copies

Philip H. Sweany, P. Sweany, 1992 .

An Experimental Evaluation of the Sufficiency of Scalar Replacement Algorithms

Philip H. Sweany, Steve Carr, Qunyan Wu, 2007 .

Trace scheduling optimization in a retargetable microcode compiler

Philip H. Sweany, Michael A. Howland, Robert A. Mueller, 1988, SIGM.