Akihiro Nitayama

发表

A spread stacked capacitor (SSC) cell for 64 Mbit DRAMs

Fumio Horiguchi, S. Inoue, Katsuhiko Hieda, 1989, International Technical Digest on Electron Devices Meeting.

A surrounding isolation-merged plate electrode (SIMPLE) cell with checkered layout for 256 Mbit DRAMs and beyond

Tohru Ozaki, Fumio Horiguchi, Katsuhiko Hieda, 1991, International Electron Devices Meeting 1991 [Technical Digest].

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Tohru Ozaki, Yuki Yamada, Tohru Furuyama, 2010, IEEE Journal of Solid-State Circuits.

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

Tohru Ozaki, Yuki Yamada, Tohru Furuyama, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2009, IEEE Transactions on Electron Devices.

Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications

Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Dynamic semiconductor memory device and method for manufacturing the same

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

A 7.4ns CMOS 16 × 16 multiplier

Yukihito Oowaki, Akihiro Nitayama, K. Numata, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A33-ns64-MbDRAM

Fumio Horiguchi, Shigeyoshi Watanabe, Kazunori Ohuchi, 1991 .

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Takashi Maeda, Akihiro Nitayama, Yoshihisa Iwata, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Three Dimensional Flash Memory with Bit Cost Scalable Technology for the Future Ultra High Density Storage Devices (Invited)

Hiroyuki Tanaka, Akihiro Nitayama, Yoshihisa Iwata, 2008 .

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1988, Technical Digest., International Electron Devices Meeting.

0.5μm CMOS technology for 5.6nsec high speed 16×16 bit multiplier

Yukihito Oowaki, Akihiro Nitayama, Hiroshi Takato, 1987, 1987 Symposium on VLSI Technology.

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs

Tohru Ozaki, Akihiro Nitayama, Ryo Fukuda, 2011, IEEE Journal of Solid-State Circuits.

A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2006, 2006 IEEE International Conference on IC Design and Technology.

Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices

Akihiro Nitayama, Hideaki Aochi, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Semiconductor memory and process for its manufacture

Fumio Horiguchi, Akihiro Nitayama, Kazumasa Sunouchi, 1990 .

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1995 .

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

Yukihito Oowaki, Shigeyoshi Watanabe, Akihiro Nitayama, 1987 .

FBC'sPotential of6F2Single CellOperation inMulti-Gbit Memories Confirmed byaNewlyDeveloped MethodforMeasuring Signal SenseMargin

Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto, 2007 .

Autonomous refresh of floating body cell (FBC)

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2008, 2008 IEEE International Electron Devices Meeting.

FBC's Potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2007, 2007 IEEE International Electron Devices Meeting.

Dynamic random access memory (RAM), and methods of making the same

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1989 .

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM

Tohru Ozaki, Akihiro Nitayama, Ryo Fukuda, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

High speed and compact CMOS circuits with multi-pillar surrounding gate transistors

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1989 .

Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices

Akihiro Nitayama, Hideaki Aochi, 2010, VLSIT 2010.

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2007, IEEE Transactions on Electron Devices.

A method of manufacturing a semiconductor memory

Fumio Horiguchi, Akihiro Nitayama, Kazumasa Sunouchi, 1990 .

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

Bit Cost Scalable (BiCS) technology for future ultra high density storage memories

Akihiro Nitayama, Hideaki Aochi, H. Aochi, 2013, 2013 Symposium on VLSI Technology.

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode

Tohru Ozaki, Akihiro Nitayama, Daisaburo Takashima, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Process Integration of Low-Power and High-Speed 16Mb MRAM using Multi-Layer Wiring Technology

S. Miura, Akihiro Nitayama, Hiroaki Yoda, 2006 .

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory

Akihiro Nitayama, Hiroaki Yoda, Tatsuya Kishi, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

A semiconductor memory device and methods for their preparation

Akihiro Nitayama, Kazumasa Sunouchi, Hiroshi Takato, 1990 .

Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory

Akihiro Nitayama, Hiroaki Yoda, Naoharu Shimomura, 2009 .

Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2008, 2008 IEEE International SOI Conference.

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Akihiro Nitayama, Takashi Ohsawa, K. Inoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

New phase shifting mask with self-aligned phase shifters for a quarter micron photolithography

Takashi Sato, Fumiaki Shigemitsu, Akihiro Nitayama, 1989, International Technical Digest on Electron Devices Meeting.

Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1990, International Technical Digest on Electron Devices.

Sub-half-micrometer concave MOSFET with double LDD structure

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1992 .

Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

Akihiro Nitayama, Takashi Ohsawa, K. Inoh, 2005, IEEE Transactions on Electron Devices.

A 33-ns 64-Mb DRAM

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1991 .