C. Thomas Gray

发表

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links

Xi Chen, Stephen G. Tell, Sudhir S. Kudva, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers

Dennis Sylvester, John W. Poulton, C. Thomas Gray, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET

Xi Chen, William J. Dally, Stephen G. Tell, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs

Benton H. Calhoun, Arijit Banerjee, Mahmut E. Sinangil, 2014, Fifteenth International Symposium on Quality Electronic Design.

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring

Xi Chen, William J. Dally, Stephen G. Tell, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Clock Period Constraints: Multiple Stage Systems

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994 .

Timing constraints for wave-pipelined systems

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Circuit delay calculation considering data dependent delays

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994, Integr..

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

William J. Dally, Stephen G. Tell, Mahmut E. Sinangil, 2016, IEEE Journal of Solid-State Circuits.

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

Xi Chen, William J. Dally, Wenxu Zhao, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects

Xi Chen, William J. Dally, Wenxu Zhao, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Wave Pipelining: Theory and CMOS Implementation

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1993 .

Clock Period Constraints: Single Stage Systems

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994 .

Practical Considerations in Wave Pipelining

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994 .

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, MICRO.

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications

Xi Chen, William J. Dally, John G. Eyles, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Hardware-Enabled Artificial Intelligence

William J. Dally, John Poulton, Brucek Khailany, 2018, 2018 IEEE Symposium on VLSI Circuits.

A DSP Based lOBaseT/lOOBaseTX Ethernet Transceiver in a l.SV, 0.18um CMOS Technology

Mark Summers, C. Thomas Gray, Scott Huss, 2001 .

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module

Wenxu Zhao, Sudhir S. Kudva, John W. Poulton, 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

Exact Timing Analysis: Algorithm

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1994 .

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications

Xi Chen, William J. Dally, John G. Eyles, 2013, IEEE Journal of Solid-State Circuits.

A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors

Benton H. Calhoun, Harsh N. Patel, Arijit Banerjee, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

Theoretical and Practical Issues in CMOS Wave Pipelining

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1991, VLSI.

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

Xi Chen, William J. Dally, Wenxu Zhao, 2019, IEEE Journal of Solid-State Circuits.

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

William J. Dally, Brucek Khailany, Nikola Nedovic, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

William J. Dally, Brucek Khailany, Stephen G. Tell, 2019, 2019 Symposium on VLSI Circuits.

Current parking regulator for zero droop/overshoot load transient response

William J. Dally, Sudhir S. Kudva, Thomas H. Greer, 2016, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC).

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET

Xi Chen, John Poulton, Nikola Nedovic, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Concurrent timing optimization of latch-based digital systems

Wentai Liu, C. Thomas Gray, Ralph K. Cavin, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

William J. Dally, Yanqing Zhang, Brucek Khailany, 2020, IEEE Journal of Solid-State Circuits.