Michele Favalli

发表

Design of CMOS self-checking sequential circuits with improved detectability of bridging faults

Cecilia Metra, Bruno Ricco, Michele Favalli, 1994 .

A probabilistic fault model for analog faults

Michele Favalli, Piero Olivo, Bruno Riccò, 1991, Proceedings of the European Conference on Design Automation..

Michele Favalli, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits

Cecilia Metra, Michele Favalli, Bruno Riccò, 2000, VLSI Design.

An experimental study of testing techniques for bridging faults in CMOS ICs

Michele Favalli, M. Lanzoni, Piero Olivo, 1993 .

On-line testing and diagnosis of bus lines with respect to intermediate voltage values (poster paper)

Cecilia Metra, Michele Favalli, Bruno Riccò, 2000, DATE '00.

Design rules for CMOS self checking circuits with parametric faults in the functional block

Cecilia Metra, Michele Favalli, Piero Olivo, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1992, Proceedings International Test Conference 1992.

Novel design for testability schemes for CMOS ICs

Michele Favalli, Piero Olivo, Bruno Ricco, 1990 .

Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1993, Proceedings of IEEE International Test Conference - (ITC).

Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits

Michele Favalli, Marcello Dalpasso, L. Valenti, 2014, IET Comput. Digit. Tech..

Functional Blocks of CMOS Self-Checking Circuits

Cecilia Metra, Michele Favalli, Piero Olivo, 1997 .

Detection of PLA multiple crosspoint faults

Michele Favalli, Piero Olivo, Bruno Riccò, 1991, Proceedings of the European Conference on Design Automation..

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults

Cecilia Metra, Michele Favalli, Bruno Riccò, 2003, Microelectron. J..

1-out-of-n dynamic CMOS checker

Cecilia Metra, Michele Favalli, 1995 .

Concurrent detection of power supply noise

Cecilia Metra, Michele Favalli, Luca Schiano, 2003, IEEE Trans. Reliab..

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

Michele Favalli, Marcello Dalpasso, 2014, J. Electron. Test..

A novel critical path heuristic for fast fault grading

Michele Favalli, Piero Olivo, Bruno Riccò, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines

Cecilia Metra, Michele Favalli, Bruno Riccò, 2000, IEEE Trans. Computers.

Testing Resistive Opens and Bridging Faults Through Pulse Propagation

Cecilia Metra, Michele Favalli, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling of broken connections faults in CMOS ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Highly testable and compact 1-out-of-n CMOS checkers

Cecilia Metra, Michele Favalli, Bruno Riccò, 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Bridging Faults in Pipelined Circuits

Cecilia Metra, Michele Favalli, C. Metra, 2000, J. Electron. Test..

Single output distributed two-rail checker with diagnosing capabilities for bus based self-checking architectures

Cecilia Metra, Michele Favalli, 2001, Proceedings Seventh International On-Line Testing Workshop.

Modeling and simulation of broken connections in CMOS IC's

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Highly testable and compact single output comparator

Cecilia Metra, Michele Favalli, Bruno Riccò, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Regression Models for Behavioral Power Estimation

Luca Benini, Giovanni De Micheli, Michele Favalli, 1998, Integr. Comput. Aided Eng..

Volcano Modelling and Simulation gateway (VMSg): A new web-based framework for collaborative research in physical modelling and simulation of volcanic phenomena

Michele Favalli, Paolo Papale, Gilberto Saccorotti, 2009 .

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices

Michele Favalli, Davide Bertozzi, Marcello Dalpasso, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

TMR voting in the presence of crosstalk faults at the voter inputs

Cecilia Metra, Michele Favalli, C. Metra, 2004, IEEE Transactions on Reliability.

Diversity analysis in the presence of delay faults affecting duplex systems

Michele Favalli, 2006, IEEE Transactions on Computers.

On the design of self-checking functional units based on Shannon circuits

Cecilia Metra, Michele Favalli, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Aliasing in signature analysis testing with multiple input shift registers

Michele Favalli, Piero Olivo, Bruno Riccò, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An analytical model for the aliasing probability in signature analysis testing

Michele Favalli, Piero Olivo, Bruno Riccò, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault simulation of parametric bridging faults in CMOS IC's

Michele Favalli, Piero Olivo, Bruno Riccò, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On-line testing scheme for clock's faults

Cecilia Metra, Michele Favalli, Bruno Riccò, 1997, Proceedings International Test Conference 1997.

Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters

Michele Favalli, Alessandro Bogliolo, Maurizio Damiani, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Symbolic Handling of Bridging Fault Effects

Michele Favalli, Marcello Dalpasso, 1997, J. Electron. Test..

Online testing approach for very deep-submicron ICs

Cecilia Metra, Michele Favalli, 2002, IEEE Design & Test of Computers.

IDDQ TEST INVALIDATION BY BREAK FAULTS

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1996 .

Testability measures in pseudorandom testing

Michele Favalli, Piero Olivo, Bruno Riccò, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Novel 1-out-of-n CMOS checker

Cecilia Metra, Bruno Ricco, Michele Favalli, 1994 .

Interactive presentation: Pulse propagation for the detection of small delay defects

Cecilia Metra, Michele Favalli, 2007 .

Test pattern generation for I/sub DDQ/: increasing test quality

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1995, Proceedings 13th IEEE VLSI Test Symposium.

An evolutionary approach to the design of on-chip pseudorandom test pattern generators

Michele Favalli, Marcello Dalpasso, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs

Michele Favalli, Daniele Ludovici, Alessandro Strano, 2013, TECS.

Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing

Cecilia Metra, Michele Favalli, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Testing scheme for IC's clocks

Cecilia Metra, Michele Favalli, C. Metra, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

Michele Favalli, Daniele Ludovici, Alessandro Strano, 2011, 2011 Design, Automation & Test in Europe.

Fault simulation of unconventional faults in CMOS circuits

Michele Favalli, Piero Olivo, Bruno Riccò, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A highly testable 1-out-of-3 CMOS checker

Cecilia Metra, Michele Favalli, Piero Olivo, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Test Pattern Generation for ID~Q: Increasing Test Quality*

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1995 .

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

Cecilia Metra, Michele Favalli, Piero Olivo, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Compact and highly testable error indicator for self-checking circuits

Cecilia Metra, Michele Favalli, Bruno Riccò, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Delay Fault Detection Problems in Circuits Feautring a Low Combination Depth

Michele Favalli, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1992, Proceedings International Test Conference 1992.

Bridging fault modeling and simulation for deep submicron CMOS ICs

Michele Favalli, Marcello Dalpasso, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A probabilistic fault model for 'analog' faults in digital CMOS circuits

Michele Favalli, Piero Olivo, Bruno Riccò, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimization of error detecting codes for the detection of crosstalk originated errors

Cecilia Metra, Michele Favalli, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Michele Favalli, Santino Mele, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Correlation between I/sub DDQ/ testing quality and sensor accuracy

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs

Michele Favalli, Bruno Riccò, L. Penza, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Analysis of resistive bridging fault detection in BiCMOS digital ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Michele Favalli, Marcello Dalpasso, 2016, IEEE Transactions on Computers.

Pulse propagation for the detection of small delay defects

Cecilia Metra, Michele Favalli, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

CMOS design for improved IC testability

Michele Favalli, Piero Olivo, Bruno Riccò, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

GMOS Checkers with Testable Bridging and Transistor Stuck-on Faults

Cecilia Metra, Michele Favalli, Piero Olivo, 1992, Proceedings International Test Conference 1992.

Fault Simulation of Parametric Bridging Faults in

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1993 .

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures

Cecilia Metra, Michele Favalli, 2002, J. Electron. Test..

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

Cecilia Metra, Michele Favalli, Piero Olivo, 1995, J. Electron. Test..

How Many Test Vectors We Need to Detect a Bridging Fault?

Michele Favalli, Marcello Dalpasso, 2009, J. Electron. Test..

Highly testable and compact 1-out-of-n code checker with single output

Cecilia Metra, Michele Favalli, Bruno Riccò, 1998, Proceedings Design, Automation and Test in Europe.

Virtual fault simulation of distributed IP-based designs

Luca Benini, Michele Favalli, Alessandro Bogliolo, 2000, DATE '00.

Signal coding technique and CMOS gates for strongly fault-secure combinational functional blocks

Cecilia Metra, Michele Favalli, Bruno Riccò, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

"Victim gate" crosstalk fault model

Michele Favalli, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Concurrent Checking of Clock Signal Correctness

Cecilia Metra, Michele Favalli, Bruno Riccò, 1998, IEEE Des. Test Comput..

Dynamic effects in the detection of bridging faults in CMOS ICs

Michele Favalli, Piero Olivo, Bruno Riccò, 1992, J. Electron. Test..

On-Chip Clock Faults' Detector

Cecilia Metra, Michele Favalli, Bruno Riccò, 2002, J. Electron. Test..

System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic

Michele Favalli, Daniele Ludovici, Davide Bertozzi, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Embedded two-rail checkers with on-line testing ability

Cecilia Metra, Michele Favalli, Bruno Riccò, 1996, Proceedings of 14th VLSI Test Symposium.

Problems due to open faults in the interconnections of self-checking data paths

Cecilia Metra, Michele Favalli, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

CMOS self checking circuits with faulty sequential functional blocks

Cecilia Metra, Michele Favalli, Bruno Riccò, 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

A fuzzy model for path delay fault detection

Michele Favalli, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design for testability of gated-clock FSMs

Luca Benini, Giovanni De Micheli, Michele Favalli, 1996, Proceedings ED&TC European Design and Test Conference.

Self-checking scheme for the on-line testing of power supply noise

Cecilia Metra, Michele Favalli, Bruno Riccò, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Switch-Level Fault Simulation by Critical-Path Tracing

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1991 .

A method for increasing the IDDQ testability

Michele Favalli, Marcello Dalpasso, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Compact and low power on-line self-testing voting scheme

Cecilia Metra, Michele Favalli, Bruno Riccò, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Analysis of glitch power dissipation in CMOS ICs

Luca Benini, Michele Favalli, 1995, ISLPED '95.

Tree checkers for applications with low power-delay requirements

Cecilia Metra, Michele Favalli, Bruno Riccò, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

Michele Favalli, Marcello Dalpasso, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Power efficiency of switch architecture extensions for fault tolerant NoC design

Michele Favalli, Alessandro Strano, Davide Bertozzi, 2012, 2012 International Green Computing Conference (IGCC).

A Method for Increasing the Testability

Michele Favalli, Marcello Dalpasso, 1997 .

On-line detection of logic errors due to crosstalk, delay, and transient faults

Cecilia Metra, Michele Favalli, Bruno Riccò, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Realistic testability estimates for CMOS ICs

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1994 .

Sensing circuit for on-line detection of delay faults

Cecilia Metra, Michele Favalli, 1996, IEEE Trans. Very Large Scale Integr. Syst..

1-out-of-3 code checker with single output

Cecilia Metra, Michele Favalli, Bruno Ricco, 1997 .

Correlation between IDDQ testing quality and sensor accuracy

Michele Favalli, Piero Olivo, Marcello Dalpasso, 1995, ED&TC.