Toshiro Hiramoto

发表

Nanoelectronics Research for Beyond CMOS Information Processing

Adrian M. Ionescu, Ken Uchida, George Bourianoff, 2010, Proc. IEEE.

Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers

Hiroshi Ohtake, Hiroshi Toshiyoshi, Yoshinori Iguchi, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Optimum design of device/circuit cooperative schemes for ultra-low power applications

Toshiro Hiramoto, 2002, Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).

Special Issue on Advanced Sub-0.1 μm CMOS Devices

Toshiro Hiramoto, 2002 .

Variable threshold CMOS (VTCMOS) in series connected circuits

Takayasu Sakurai, Toshiro Hiramoto, Takashi Inukai, 2001, ISLPED '01.

Emerging nanoscale silicon devices taking advantage of nanostructure physics

Masumi Saitoh, Toshiro Hiramoto, Gen Tsutsui, 2006, IBM J. Res. Dev..

Three-Layered Stacking Process by Au/SiO 2 Hybrid Bonding for 3D Structured Image Sensors

Hiroshi Toshiyoshi, Yoshinori Iguchi, Yuki Honda, 2017 .

Pixel-Parallel 3D Integrated CMOS Image Sensors Developed by Direct Bonding of SOI Layers for Next-Generation Video Systems

Hiroshi Toshiyoshi, Yoshinori Iguchi, Yuki Honda, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

Takayasu Sakurai, Toshiro Hiramoto, Takashi Inukai, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress

Anil Kumar, Toshiro Hiramoto, Takuya Saraya, 2013, IEICE Trans. Electron..

Optimum Device Parameters and Scalability of Variable Threshold CMOS (VTCMOS)

Takayasu Sakurai, Makoto Takamiya, Toshiro Hiramoto, 2000 .

Integrated Circuits: 50 Years of Their Evolution and Future Prospects ―Towards Higher-Density Memories and Ultra-Low Power LSIs―

Kenji Taniguchi, Takayasu Sakurai, Toshiro Hiramoto, 2013 .

Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs

Anil Kumar, Toshiro Hiramoto, Takuya Saraya, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

Ichiro Omura, Hiroshi Iwai, M. Kobayashi, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Measurement of SRAM Power-up Data using an Addressable Cell Array Test Structure

Hirofumi Shinohara, Toshiro Hiramoto, Takuya Saraya, 2016 .

Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2016, IEEE Transactions on Electron Devices.

Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2016, 2016 International Conference on Microelectronic Test Structures (ICMTS).

Effects of Discrete Quantum Levels on Electron Transport in Silicon Single-Electron Transistors with an Ultra-Small Quantum Dot

Masumi Saitoh, Toshiro Hiramoto, 2001 .

Contactless actuation of giant magnetostriction thin-film alloy bimorphs for two-dimensional scanning application

Hiroyuki Fujita, Toshiro Hiramoto, Dominique Givord, 1997, Photonics West - Micro and Nano Fabricated Electromechanical and Optical Components.

Parallel nonvolatile programming of power-up states of SRAM cells

Masaharu Kobayashi, Toshiro Hiramoto, Kiyoshi Takeuchi, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Hirofumi Shinohara, Toshiro Hiramoto, Takuya Saraya, 2017 .

A Bipolar-Based 0.5μm BiCMOS Technology on Bonded SOI for High-Speed LSIs (Special Section on High Speed and High Density Multi Functional LSI Memories)

Nobuo Tamba, Makoto Yoshida, Kunihiko Watanabe, 1994 .

Experimental Demonstration of a Nonvolatile SRAM With Ferroelectric HfO2 Capacitor for Normally Off Application

Masaharu Kobayashi, Toshiro Hiramoto, Nozomu Ueyama, 2018, IEEE Journal of the Electron Devices Society.

Measurement of Static Random Access Memory Power-Up State Using an Addressable Cell Array Test Structure

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2017, IEEE Transactions on Semiconductor Manufacturing.

Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs

Anil Kumar, Toshiro Hiramoto, Tomoko Mizutani, 2013, IEICE Trans. Electron..

Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations

Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, 2007, IEICE Trans. Electron..

A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

Kunihiko Yamaguchi, H. Nambu, Nobuo Tamba, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A new write stability metric using extended write butterfly curve for yield estimation in SRAM cells at low supply voltage

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2016, 2016 International Conference on Microelectronic Test Structures (ICMTS).

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps

Adrian M. Ionescu, Ken Uchida, George Bourianoff, 2010, Proceedings of the IEEE.

Variability in Scaled MOS Transistors: Present Status and Measures

Toshiro Hiramoto, Kiyoshi Takeuchi, Akio Nishida, 2008 .

Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias

Makoto Takamiya, Toshiro Hiramoto, T. Hiramoto, 2000 .

Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel Signal Processors

Hiroshi Ohtake, Hiroshi Toshiyoshi, Yoshinori Iguchi, 2015 .

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

Takayasu Sakurai, Toshiro Hiramoto, Takashi Inukai, 2001, ISLPED '01.

Vth self-adjusting tri-gate nanowire MOSFET for stability improvement of SRAM cell operating at 0.1 V

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

In-pixel A/D converters with 120-dB dynamic range using event-driven correlated double sampling for stacked SOI image sensors

Hiroshi Toshiyoshi, Yuki Honda, Eiji Higurashi, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

研究解説 : Joint Research on Micromechatronics between the "Centre National de la Recherche Scientifique (CNRS)" and the "Institute of Industrial Science (IIS)"

Hideki Hashimoto, Hannes Bleuler, Toshiro Hiramoto, 1995 .

11-3 Development of elemental technology for 3D-integrated image sensors

Hiroshi Ohtake, Hiroshi Toshiyoshi, Yoshinori Iguchi, 2013 .

A redundancy technique for ultra-high-speed SRAMs

Youji Idei, H. Nambu, Kazuo Kanetani, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration

Takayasu Sakurai, Makoto Takamiya, Toshiro Hiramoto, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration

Hiroshi Toshiyoshi, Yoshinori Iguchi, Yuki Honda, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Session #5 SOI photonics, MEMS, sensors, and circuits

Dong-Won Kim, Toshiro Hiramoto, 2008 .

(Invited) Pixel-Parallel 3-D Integrated CMOS Image Sensors for Next-Generation Video Systems

Hiroshi Toshiyoshi, Yoshinori Iguchi, Yuki Honda, 2018 .

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Nobuyuki Sugii, Koichiro Ishibashi, Toshiro Hiramoto, 2014 .

Statistical analysis of four write stability metrics in fully depleted silicon-on-thin-BOX (SOTB) and bulk SRAM cells at low supply voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

(Invited) Development of Novel Three-Dimensional Structuring of Integrated Circuits by Using Low Temperature Direct Bonding for CMOS Image Sensors

Hiroshi Ohtake, Hiroshi Toshiyoshi, Yoshinori Iguchi, 2014 .

Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary]

Toshiro Hiramoto, Kosmas Galatsis, Joachim Pelka, 2015, IEEE Technol. Soc. Mag..

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

Guiding Principles for Ultimate Integrated Systems – Discussions in the JSPS 165th Committee –

Toshiro Hiramoto, 2015 .

ED2000-124 / SDM2000-106 / ICD2000-60 Boosted Gate MOS(BGMOS):Leakage-Free Circuits by Device/Circuit Cooperation Scheme

Takayasu Sakurai, Makoto Takamiya, Toshiro Hiramoto, 2000 .

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM

Anil Kumar, Toshiro Hiramoto, Takuya Saraya, 2013, IEICE Trans. Electron..

Ultra-low-voltage operation: Device perspective

Toshiro Hiramoto, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Prospect and International Collaboration in Nanoelectronics

Toshiro Hiramoto, 2014 .

Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs

Toshiro Hiramoto, Takuya Saraya, H. Majima, 2002 .

Comparison and Statistical Analysis of Four Write Stability Metrics in Bulk CMOS SRAM Cells

Toshiro Hiramoto, Takuya Saraya, Tomoko Mizutani, 2014 .

Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETs

Toshiro Hiramoto, Takuya Saraya, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

(Invited) Pixel-Parallel CMOS Image Sensors with 16-Bit A/D Converters Developed by 3-D Integration of SOI Layers with Au/SiO2 Hybrid Bonding

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2016 .

Time, 78-pm' Memory-Cell Size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, Kenichi Ohhata, 1992 .

High-speed sensing techniques for ultrahigh-speed SRAMs

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

Random Fluctuations in Scaled MOS Devices

Toshiro Hiramoto, Kiyoshi Takeuchi, Akio Nishida, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Variation; key issue of the advanced CMOS & LSI's

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Quarter Video Graphics Array Digital Pixel Image Sensing With a Linear and Wide- Dynamic-Range Response by Using Pixel-Wise 3-D Integration

Hiroshi Toshiyoshi, Yoshinori Iguchi, Yuki Honda, 2019, IEEE Transactions on Electron Devices.

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Mechanical characterization of magnetostrictively actuated microresonators

Hiroyuki Fujita, Tarik Bourouina, Toshiro Hiramoto, 1999, Smart Materials, Nano-, and Micro- Smart Systems.

Development of a three-dimensional integrated image sensor with pixel-parallel signal processing architecture

Hiroshi Ohtake, Hiroshi Toshiyoshi, Yoshinori Iguchi, 2015, 2015 IEEE SENSORS.

Toward 0.1V operation of MOSFETs for ultra-low power applications

Toshiro Hiramoto, Takuya Saraya, Seung-Min Jung, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately

Ken Takeuchi, Kuniyuki Kakushima, Toshiro Hiramoto, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

Ken Takeuchi, Hiroshi Iwai, Kuniyuki Kakushima, 2018, 2018 IEEE Symposium on VLSI Circuits.

Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

Toshiro Hiramoto, Takuya Saraya, Masaharu Kobayashi, 2016 .

Characteristics control of room-temperature operating single electron transistor with floating gate by charge pump circuit

Toshiro Hiramoto, Takuya Saraya, Ryota Suzuki, 2013 .

Analytical model of body factor in short channel bulk MOSFETs for low voltage applications

Anil Kumar, Toshiro Hiramoto, Gen Tsutsui, 2004 .

Analysis of delay time in subthreshold CMOS circuits operating at ultra-low supply voltage

Toshiro Hiramoto, Takuya Saraya, Seung-Min Jung, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).

A Feasibility Study on Ferroelectric Shadow SRAMs Using a New Variability Design Scheme

Masaharu Kobayashi, Toshiro Hiramoto, Kiyoshi Takeuchi, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Floating body effects in 0.15 /spl mu/m partially depleted SOI MOSFETs below 1 V

Toshiaki Ikoma, Hiroki Ishikuro, Makoto Takamiya, 1996, 1996 IEEE International SOI Conference Proceedings.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Variable threshold voltage CMOS (VTCMOS) in series connected circuits

Takayasu Sakurai, Toshiro Hiramoto, Takashi Inukai, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

Recent Progress of Double/Dual-Gate Silicon IGBT Technologies

Toshiro Hiramoto, Takuya Saraya, 2021, 2021 IEEE 14th International Conference on ASIC (ASICON).

Optimum Device Consideration for Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)

Takayasu Sakurai, Toshiro Hiramoto, T. Sakurai, 2002 .

Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2009 .

Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness-Multiple Threshold Voltage CMOS (DOT-MTCMOS)

Toshiro Hiramoto, Takashi Inukai, 2000 .

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2002 .

Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

Masumi Saitoh, Toshiro Hiramoto, Kousuke Miyaji, 2006 .

Three-Dimensional Integration of Fully Depleted Silicon-on-Insulator Transistor Substrates for CMOS Image Sensors Using Au/SiO2 Hybrid Bonding and XeF2 Etching

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2014 .

Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots

Masumi Saitoh, Toshiro Hiramoto, Takashi Inukai, 2001 .

Suppression of Stand-By Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCM

Toshiro Hiramoto, Takashi Inukai, 1999 .

Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot

Akio Nishida, Toshiro Hiramoto, Takaaki Tsunomura, 2010 .

Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering

Takayasu Sakurai, Toshiro Hiramoto, Qingyan Liu, 2003 .

Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs

Toshiro Hiramoto, Gen Tsutsui, Toshiharu Nagumo, 2003 .

Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain

Masumi Saitoh, Toshiro Hiramoto, Kousuke Miyaji, 2005 .

Coulomb blockade oscillations at room temperature in a Si quantum wire metal‐oxide‐semiconductor field‐effect transistor fabricated by anisotropic etching on a silicon‐on‐insulator substrate

Toshiro Hiramoto, Takuya Saraya, Gen Hashiguchi, 1996 .

A nonvolatile SRAM integrated with ferroelectric HfO2 capacitor for normally-off and ultralow power IoT application

Masaharu Kobayashi, Toshiro Hiramoto, Nozomu Ueyama, 2017, 2017 Symposium on VLSI Technology.

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Nobuyuki Sugii, Toshiro Hiramoto, Hidekazu Oda, 2008 .

Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs

Makoto Takamiya, Toshiro Hiramoto, Hiroshi Koura, 1999 .

Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

Masumi Saitoh, Toshiro Hiramoto, Kosuke Yanagidaira, 2005 .

Superior mobility characteristics in [110]-oriented ultra thin body pMOSFETs with SOI thickness less than 6 nm

Masumi Saitoh, Toshiro Hiramoto, Gen Tsutsui, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Impact of the device scaling on the low-frequency noise in n-MOSFETs

Toshiro Hiramoto, H. Majima, Youliao Zheng, 2000 .

6.3 A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology

Hiroshi Kawaguchi, Kouichi Kanda, Takayasu Sakurai, 2003 .

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2018 .

Magnetic actuation of bending and torsional vibrations for 2D optical-scanner application

Hiroyuki Fujita, Tarik Bourouina, Toshiro Hiramoto, 2000 .

Mechanical grinding of Au/SiO2 hybrid-bonded substrates for 3D integrated image sensors

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2014, 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D).

Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2010 .

Future Electron Devices and SOI Technology ?Semi-Planar SOI MOSFETs with Sufficient Body Effect?

Toshiro Hiramoto, Toshiharu Nagumo, Toshiki Saito, 2003 .

High drive-current electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltage

Makoto Takamiya, Toshiro Hiramoto, 1998 .

128 × 96 Pixel-parallel three-dimensional integrated CMOS image sensors with 16-bit A/D converters: By direct bonding with embedded Au electrodes

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

Makoto Takamiya, Toshiro Hiramoto, Takuya Saraya, 1998 .

Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor

Masumi Saitoh, Toshiro Hiramoto, Nobuyoshi Takahashi, 2001 .

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Akio Nishida, Toshiro Hiramoto, Kiyoshi Takeuchi, 2009 .

A novel MOSFET with vertical signal‐transfer capability for 3D‐structured CMOS image sensors

Hiroshi Toshiyoshi, Yoshinori Iguchi, Toshiro Hiramoto, 2014 .

High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2011 .

Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

Nobuyuki Sugii, Toshiro Hiramoto, Hidekazu Oda, 2009 .

Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs

Toshiro Hiramoto, T. Ohtou, Toshiharu Nagumo, 2004 .

Negative Capacitance for Boosting Tunnel FET performance

Masaharu Kobayashi, Toshiro Hiramoto, Nozomu Ueyama, 2017, IEEE Transactions on Nanotechnology.

Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2015, IEEE Transactions on Electron Devices.

Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin

Toshiro Hiramoto, Fumihiko Tachibana, 2004 .

Comparison of statistical distributions of random telegraph noise (RTN) in subthreshold region and strong inversion region

Toshiro Hiramoto, Takuya Saraya, Tomoko Mizutani, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).

Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: Operation speed, material requirement and energy efficiency

Masaharu Kobayashi, Toshiro Hiramoto, T. Hiramoto, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal-Oxide-Semiconductor Field-Effect Transistors in 45 nm Technology and Beyond

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2009 .

Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and single-electron transistors

Masaharu Kobayashi, Toshiro Hiramoto, T. Hiramoto, 2008 .

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs and Bulk MOSFETs

Nobuyuki Sugii, Toshiro Hiramoto, Hideki Makiyama, 2012 .

Correlation between static random access memory power-up state and transistor variation

Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto, 2017 .

On gate stack scalability of Double-Gate Negative-Capacitance FET with ferroelectric HfO2 for energy-efficient sub-0.2V operation

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group

Akio Nishida, Toshiro Hiramoto, Takaaki Tsunomura, 2009 .

Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor

Masumi Saitoh, Toshiro Hiramoto, 2004 .

Variable Body Effect Factor FD SOI MOSFET for Ultra-Low Power VTCMOS Applications

Toshiro Hiramoto, T. Ohtou, Toshiharu Nagumo, 2003 .

Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)

Hiroshi Kawaguchi, Takayasu Sakurai, Makoto Takamiya, 2001 .

Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS

Toshiro Hiramoto, Takashi Inukai, Hyunsik Im, 2001 .

Transistor-level Characterization of SRAM Bit Failures Induced by Random Telegraph Noise

Masaharu Kobayashi, Toshiro Hiramoto, Takuya Saraya, 2015 .

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Nobuyuki Sugii, Hirofumi Shinohara, Toshiro Hiramoto, 2014 .

Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2004 .

Separation of effects of statistical impurity number fluctuations and position distribution on Vth fluctuations in scaled MOSFETs

Makoto Takamiya, Toshiro Hiramoto, Yuri Yasuda, 2000 .

Quantum mechanical effects in the silicon quantum dot in a single-electron transistor

Toshiro Hiramoto, T. Hiramoto, H. Ishikuro, 1997 .

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

Anil Kumar, Toshiro Hiramoto, Tomoko Mizutani, 2012 .

Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor

Masumi Saitoh, Toshiro Hiramoto, Takashi Inukai, 2001 .

Threshold voltage fluctuations induced by statistical ‘position’ and ‘number’ impurity fluctuations in bulk MOSFETs

Makoto Takamiya, Toshiro Hiramoto, Yuri Yasuda, 2000 .

Measuring threshold voltage variability of 10G transistors

Anil Kumar, Toshiro Hiramoto, Tomoko Mizutani, 2011, 2011 International Electron Devices Meeting.

Room-temperature demonstration of highly-functional single-hole transistor logic based on quantum mechanical effect

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2004 .

Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range

Toshiro Hiramoto, Takuya Saraya, Jiezhi Chen, 2010, 2010 Symposium on VLSI Technology.

Variable Body Effect Factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor for Ultra Low-Power Variable-Threshold-Voltage Complementary Metal Oxide Semiconductor Applications

Toshiro Hiramoto, T. Ohtou, Toshiharu Nagumo, 2004 .

Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode

Nobuyuki Sugii, Toshiro Hiramoto, Toshiaki Iwamatsu, 2008 .

Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Toshiro Hiramoto, Yi Shi, T. Hiramoto, 1998 .

3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2 Hybrid Bonding

Hiroshi Toshiyoshi, Yoshinori Iguchi, Eiji Higurashi, 2014, IEEE Transactions on Electron Devices.

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

Masayuki Ohayashi, Kunihiko Yamaguchi, H. Nambu, 1994 .

Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs

Makoto Takamiya, Toshiro Hiramoto, Hiroshi Koura, 2000 .

Process Condition Dependence of Random V T Variability in NFETs and PFETs

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2009 .

Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors

Makoto Takamiya, Toshiro Hiramoto, Takuya Saraya, 1999 .

Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin

Toshiro Hiramoto, Fumihiko Tachibana, 2005 .

Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors

Masumi Saitoh, Toshiro Hiramoto, T. Hiramoto, 2005 .

Future Electron Devices and SOI Technology

Toshiro Hiramoto, Toshiharu Nagumo, T. Hiramoto, 2002 .

Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

Nobuyuki Sugii, Tomohiro Yamashita, Toshiro Hiramoto, 2015 .

Low-power device design of fully-depleted SOI MOSFETs

Toshiro Hiramoto, T. Ohtou, Toshiharu Nagumo, 2003, International Semiconductor Device Research Symposium, 2003.