Sueyoshi Toshinori

发表

A low-power clustering tool using both routability and activity for FPGAs

Eto Junya, Amagasaki Motoki, Iida Masahiro, 2009 .

A Context Design Method to Improve Power Efficiency for Reconfigurable Logic Device

Iida Masahiro, Sueyoshi Toshinori, Shinohara Hiroshi, 2007 .

An Area Optimization of 3D FPGA with high speed inter-layer communication link

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

Prototype of fault tolerant FPGA using 65nm CMOS process

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2014 .

A case study of an FPGA implementation for streaming data filtering

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2019 .

Recovery and syncronization technique for TMR softcore processor

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2009 .

Adoption and Evaluation of FPGA Partial Reconfiguration for a Run-time Reconfigurable System

Sueyoshi Toshinori, Kuga Morihiro, Kiyota Yukinobu, 2007 .

Panel Discussion : How Will VLSI Processors and System LSIs Change in Future?

和彰村上, Sueyoshi Toshinori, Murakami Kazuaki, 1997 .

Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

Multi bit soft error tolerant FPGA architecture

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2016 .

Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2017 .

An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

Visibility study of CNN implementation using High Speed Serial Optical Interconnection

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2018 .

Context Synchronization Method for Reliable Softcore Processor System

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2011 .

Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

An optimization method for MIMD controlled data communication of MX Core

Iida Masahiro, Sueyoshi Toshinori, Kodama Akihiro, 2008 .

A Design Framework for Reconfigurable IPs with VLSI CADs

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2012 .

Implementation of Basic Function Blocks for Variable Grain Logic Cell

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2005 .

Resources Utilization of Fine-grained Overlay Architecture

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2018 .

Fast soft-error recovery method for duplicated softcore processor system

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Formal Description of Synchronization by Functional Definition of Synchronous Circuits

Amagasaki Motoki, Sueyoshi Toshinori, Nishimura Shunji, 2016 .

CNN implementation on FPGA with Power of 2 Approximation of Weight

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2017 .

A hardware description method and sematics providing a timing constrant

Amagasaki Motoki, Sueyoshi Toshinori, Nishimura Shunji, 2014 .

Optimization method of data communication PEs for Massively Parallel SIMD processor

Iida Masahiro, Sueyoshi Toshinori, Kodama Akihiro, 2008 .

A Basic Study of FPGA Routing Architecture Based on Scale Free Network

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

FPGA placement based on Self-Organized Map

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Fault Recovery Technique for Softcore Processor using Partial Reconfiguration

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2010 .

hCODE 2.0: An Open-source Platform for FPGA Cluster System

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2017 .

A design of FPGA routing structure with Switch-Block-cum-Shifter

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Examination of the virtual wiring for an ASIC emulator using high-speed serial communication

Sueyoshi Toshinori, Kuga Morihiro, Ichinomiya Yoshihiro, 2010 .

Hard error avoidance for TMR module using dynamic relocation in an FPGA

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

A case study of the effective value range analysis for Behavioral synthesis

Sueyoshi Toshinori, Kuga Morihiro, Tomonaga Kenji, 2010 .

Development of Inter-module Communication Mechanism for Dynamically Reconfigurable System

Sueyoshi Toshinori, Kuga Morihiro, Yatsunami Taiichiro, 2007 .

A Study of Methodology and Tools for Open-source FPGA Accelerators

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2016 .

A Study of Local Interconnect Architecture for Variable Grain Logic Cell

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2008 .

An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2010 .

Functionally-partitioned JPEG decoder for partial dynamic reconfiguration

Sueyoshi Toshinori, Kuga Morihiro, Yatsunami Taiichiro, 2008 .

Development of clustering tool to reduce area of chip and delay

Iida Masahiro, Sueyoshi Toshinori, Kobata Masaki, 2005 .

The Effect of Variable Grain Logic Cell Functionality on Area

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2007 .

A case study of High-level Synthesis Using Higher-order Function on Functional Language

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2017 .

A Case Study on Complex Event Processing over low cost ARM+FPGA Boards.

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2018 .

Reliability Management in 2-layered Supervisor Processor

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

A Study of Mapping Method for Variable Grain Logic Cell Architecture

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2006 .

A case study of database filtering on streaming processing

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2018 .

A Case Study of Duplication Technique for SRAM-based FPGA

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2010 .

An Implementation Technique for Variable Grain Logic Cell to Reduce Delay and Configuration Memories

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2007 .

A study of run-time fault detection mechanism for fault-tolerant FPGAs

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2014 .

A study on reconfigurable direct conversion JAVA accelerator for embedded systems

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

An Implementation of Ant Colony Optimization for the MaTriX Processing Engine

Iida Masahiro, Sueyoshi Toshinori, Nakano Mitsutaka, 2006 .

Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic

Amagasaki Motoki, Sueyoshi Toshinori, Nishimura Shunji, 2014 .

A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2007 .

FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2018 .

A Case Study of Functionally-Distributed Dual Processor System on an FPGA

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2009 .

An example of function sharing implementation for reconfigurable systems

Sueyoshi Toshinori, Kuga Morihiro, Kiyota Yukinobu, 2006 .

Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core

Iida Masahiro, Sueyoshi Toshinori, Mizokami Yuta, 2009 .

A case study of efficient task scheduling for FPGA-based partially reconfigurable systems

Sueyoshi Toshinori, Kuga Morihiro, Tsutsumi Yoshiaki, 2010 .

Development of an FPGA Board toward Reconfigurable Cluster Computing

Iida Masahiro, Sueyoshi Toshinori, Kuga Morihiro, 2005 .

Trax solver based on machine-learned evaluation function

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .

A Novel Abridged Adaptive LUT Architecture with Few Configulation Memories

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

A Technology Mapping Method for Scalable Logic Module

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

A implementation of RSA encryption using Interleaved Modular Multiplication for MX Core

Iida Masahiro, Sueyoshi Toshinori, Kuroki Wataru, 2009 .

Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Advantages of Variable Grain Logic Cell Architecture

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2006 .

A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs.

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2010 .

Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .

Three-dimensional FPGA Structure using High-speed Serial Communication

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2014 .

An Area Minimized Logic Cluster using COGRE Logic Cell

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

Routing Performance Evaluation for Stationary End Nodes in Ad Hoc Network

Sueyoshi Toshinori, Nakashima Takuo, 2007 .

A proposal of Bit Serial Arithmetic Units for Arbitrary Precision

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2017 .

A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2009 .

First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2010 .

Exploration of Input Granularity Optimization for Variable Grain Logic Cell

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2008 .

A Novel Cluster Structure based on Input Sharing of LUTs

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Path Planning Method for MIMD Controlled data communication in MX Core

Iida Masahiro, Sueyoshi Toshinori, Kodama Akihiro, 2008 .

SOM Based FPGA Placement Method Considering Wire Segment Length

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .

A Study of HW/SW Co-design Framework based on the Virtualization Technology

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2015 .

A Homogeneous Routing Architecture for Efficient FPGA Design

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

A Study of Performance-driven Simultaneous Clustering and Placement for FPGA

Iida Masahiro, Sueyoshi Toshinori, Shinohara Hiroshi, 2007 .

An Implementation and evaluation of Ant Colony Optimization for massively parallel SIMD processor MX Core

Iida Masahiro, Sueyoshi Toshinori, Nakano Mitsutaka, 2007 .

A Low-Power Technique using Resource Sharing Approach for Multi-Context Device

Iida Masahiro, Sueyoshi Toshinori, Shinohara Hiroshi, 2006 .

An examination of hardware acceleration in FPGA placement based on SA

Sueyoshi Toshinori, Kuga Morihiro, Sonokawa Yoshio, 2007 .

Parallelization of the channel width search for FPGA routing

Sueyoshi Toshinori, Kuga Morihiro, Sawada Hiroomi, 2011 .

Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2017 .

A Comparison of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2014 .

Relocation of Partial Reconfiguration Data for Dynamic Reconfigurable System

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

FPGA routing structure based on H-Tree topology

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2016 .

Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System

Iida Masahiro, Sueyoshi Toshinori, Kuga Morihiro, 2005 .

Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2014 .

A LUT Architecture Based on Partial Function of Shannon Expansion

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .

Looking Back over My Researches on Flexible Hardware -- Reconfigurable Systems and FPGAs

Sueyoshi Toshinori, 2014 .

Mapping of Java bytecode to virtual CGRA with implementation in FPGA

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .

A performance evaluation of Matrix Processing Engine for media applications

Iida Masahiro, Sueyoshi Toshinori, Kuga Morihiro, 2006 .

A Case Study of Reliable Softcore Processor Using TMR Technique

Amagasaki Motoki, Sueyoshi Toshinori, Kuga Morihiro, 2008 .

A performance evaluation of SIMD type accelerator for JPEG2000 application

Iida Masahiro, Sueyoshi Toshinori, Kuga Morihiro, 2005 .

A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2011 .

Development of power estimation tool for three dimensional FPGA

Zhao Qian, Amagasaki Motoki, Iida Masahiro, 2016 .

SOM-based FPGA Placement Method using Shimbel Index

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2012 .

Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs

Iida Masahiro, Sueyoshi Toshinori, Nishioka Yuzo, 2008 .

A defect-robust FPGA-IP core architecture

Amagasaki Motoki, Iida Masahiro, Sueyoshi Toshinori, 2013 .