H. Chigasaki

A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

K. Nii, H. Fujiwara, Y. Kihara, 2010, 2010 Symposium on VLSI Circuits.

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

Hidehiro Fujiwara, Koji Nii, Kazumasa Yanagisawa, 2010 .