Cliff C. N. Sze

发表

Ispd2009 clock network synthesis contest

Gi-Joon Nam, Charles J. Alpert, Cliff C. N. Sze, 2009, ISPD '09.

A methodology for propagating design tolerances to shape tolerances for use in manufacturing

Sani R. Nassif, Michael Orshansky, Shayak Banerjee, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Routing congestion estimation with real design constraints

Yih-Lang Li, Wen-Hao Liu, Natarajan Viswanathan, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Pyramids: An efficient computational geometry-based approach for timing-driven placement

David Z. Pan, Charles J. Alpert, Zhuo Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Igor L. Markov, Gi-Joon Nam, Charles J. Alpert, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

Igor L. Markov, Natarajan Viswanathan, Gi-Joon Nam, 2011, IEEE Micro.

CATALYST: Planning layer directives for effective design closure

Shiyan Hu, Sachin S. Sapatnekar, Charles J. Alpert, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Quantifying academic placer performance on custom designs

Earl E. Swartzlander, Charles J. Alpert, Samuel I. Ward, 2011, ISPD '11.

Buffering in the Layout Environment

Jiang Hu, Cliff C. N. Sze, 2008, Handbook of Algorithms for Physical Design Automation.

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Yici Cai, Qiang Zhou, Hailong Yao, 2011, GLSVLSI '11.

Porosity-aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Cliff C. N. Sze, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ISPD 2013 expert designer/user session (eds)

Mark Zwolinski, Laleh Behjat, Cliff C. N. Sze, 2013, ISPD '13.

Challenges of cell selection algorithms in industrial high performance microprocessor designs

Tiago Reimann, Ricardo Reis, Cliff C. N. Sze, 2016, Integr..

Navigating Register Placement for Low Power Clock Network Design

Yongqiang Lyu, Yici Cai, Qiang Zhou, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A place and route aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Cliff C. N. Sze, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Multilevel circuit clustering for delay minimization

Ting-Chi Wang, Li-C. Wang, Cliff C. N. Sze, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The future of clock network synthesis

Cliff C. N. Sze, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Yongqiang Lyu, Yici Cai, Qiang Zhou, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Path-Based Buffer Insertion

Jiang Hu, Weiping Shi, Charles J. Alpert, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design methodology for the IBM POWER7 microprocessor

Haifeng Qian, Shyam Ramji, Joachim Keinert, 2011, IBM J. Res. Dev..

Shedding Physical Synthesis Area Bloat

Louise Trevillyan, Charles J. Alpert, Zhuo Li, 2011, VLSI Design.

GPU acceleration for Bayesian control of Markovian genetic regulatory networks

Jiang Hu, Frank Liu, Mohammadmahdi R. Yousefi, 2016, 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI).

Optimal circuit clustering for delay minimization under a more general delay model

Ting-Chi Wang, Cliff C. N. Sze, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Grid-to-ports clock routing for high performance microprocessor designs

Evangeline F. Y. Young, Cliff C. N. Sze, Haitong Tian, 2011, ISPD '11.

Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo

Sani R. Nassif, Cliff C. N. Sze, William Evan Speight, 2013, ICCS.

GLARE: Global and local wiring aware routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2012, DAC Design Automation Conference 2012.

Timing-driven Steiner trees are (practically) free

Andrew B. Kahng, Charles J. Alpert, Cliff C. N. Sze, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Navigating registers in placement for clock network minimization

Yongqiang Lyu, Yici Cai, Qiang Zhou, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Fast and Highly Scalable Bayesian MDP on a GPU Platform

Jiang Hu, Frank Liu, He Zhou, 2017, BCB.

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Igor L. Markov, Gi-Joon Nam, Charles J. Alpert, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improved alternative wiring scheme applying dominator relationship

Yu-Liang Wu, Cliff C. N. Sze, 2001, ASP-DAC '01.

WRIP: logic restructuring techniques for wirelength-driven incremental placement

Yu-Liang Wu, Charles J. Alpert, Cliff C. N. Sze, 2012, GLSVLSI '12.

Cell Selection for High-Performance Designs in an Industrial Design Flow

Tiago Reimann, Ricardo Reis, Cliff C. N. Sze, 2016, ISPD.

Performance-driven multi-level clustering for combinational circuits

Ting-Chi Wang, Cliff C. N. Sze, 2003, ASP-DAC '03.

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results

Cliff C. N. Sze, 2010, ISPD '10.

Algorithms for the scaling toward nanometer VLSI physical synthesis

Cliff C. N. Sze, 2007 .

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Ozgur Sinanoglu, Jens Lienig, Ibrahim M. Elfadel, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Wire synthesizable global routing for timing closure

Cliff C. N. Sze, Michael D. Moffitt, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Gate sizing and threshold voltage assignment for high performance microprocessor designs

Tiago Reimann, Ricardo Reis, Cliff C. N. Sze, 2015, The 20th Asia and South Pacific Design Automation Conference.

The ISPD global routing benchmark suite

Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz, 2008, ISPD '08.

The ISPD-2011 routability-driven placement contest and benchmark suite

Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, 2011, ISPD '11.

Timing-Driven Interconnect Synthesis

Jiang Hu, Gabriel Robins, Cliff C. N. Sze, 2008, Handbook of Algorithms for Physical Design Automation.

Placement: Hot or Not?

Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Skew scheduling and clock routing for improved tolerance to process variations

Jiang Hu, Ganesh Venkataraman, Cliff C. N. Sze, 2005, ASP-DAC.

Proceedings of the 2019 International Symposium on Physical Design

Azadeh Davoodi, Cliff C. N. Sze, 2019, ISPD.

Postgrid Clock Routing for High Performance Microprocessor Designs

Evangeline F. Y. Young, Cliff C. N. Sze, Haitong Tian, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Yu-Liang Wu, Charles J. Alpert, Cliff C. N. Sze, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Making fast buffer insertion even faster via approximation techniques

Jiang Hu, Weiping Shi, Charles J. Alpert, 2005, ASP-DAC.

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite

Natarajan Viswanathan, Charles J. Alpert, Zhuo Li, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Yici Cai, Qiang Zhou, Hailong Yao, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Techniques for Fast Physical Synthesis

Gi-Joon Nam, Charles J. Alpert, Zhuo Li, 2007, Proceedings of the IEEE.

Proceedings of the 2013 ACM international symposium on International symposium on physical design

Cheng-Kok Koh, Cliff C. N. Sze, 2012, ISPD 2013.

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes

Azadeh Davoodi, Muhammet Mustafa Ozdal, Jiang Hu, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Challenges and Future Directions of 3D Physical Design

Jens Lienig, Johann Knechtel, Cliff C. N. Sze, 2017 .

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Shiyan Hu, Weiping Shi, Charles J. Alpert, 2010, ISPD '10.

Optimal circuit clustering with variable interconnect delay

Ting-Chi Wang, Cliff C. N. Sze, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Techniques for scalable and effective routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2014, TODE.

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design

Cheng-Kok Koh, Cliff C. N. Sze, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The nuts and bolts of physical synthesis

Gi-Joon Nam, Charles J. Alpert, Zhuo Li, 2007, SLIP '07.

Clock power minimization using structured latch templates and decision tree induction

David Z. Pan, Natarajan Viswanathan, Charles J. Alpert, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

The DAC 2012 routability-driven placement contest and benchmark suite

Natarajan Viswanathan, Charles J. Alpert, Zhuo Li, 2012, DAC Design Automation Conference 2012.

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, 2012, DAC Design Automation Conference 2012.