Kiyeon Lee

Accurately modeling superscalar processor performance with reduced trace

Sangyeun Cho, Kiyeon Lee, Sangyeun Cho, 2013, J. Parallel Distributed Comput..

Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach

Hyunjin Lee, Sangyeun Cho, Kiyeon Lee, 2010, Softw. Pract. Exp..

Modeling Out-of-Order Superscalar Processor Performance Quickly and Accurately with Traces

Kiyeon Lee, Kiyeon Lee, 2013 .

Accurately approximating superscalar processor performance from traces

Sangyeun Cho, Kiyeon Lee, Shayne Evans, 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems

Sangyeun Cho, Kiyeon Lee, Lei Jin, 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing

Sangyeun Cho, Kiyeon Lee, Taecheol Oh, 2011, 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems.

In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces

Sangyeun Cho, Kiyeon Lee, Sangyeun Cho, 2011, 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems.

Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors

Soojung Ryu, Moo-Kyoung Chung, Sangyeun Cho, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation

Hyunjin Lee, Sangyeun Cho, Kiyeon Lee, 2008, 2008 37th International Conference on Parallel Processing.

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach

Hyunjin Lee, Sangyeun Cho, Kiyeon Lee, 2010 .

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

Sangyeun Cho, Kiyeon Lee, Taecheol Oh, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.