M. Ino

Sub-fJ inverter analysis for GaAs VLSI

M. Togashi, M. Hirayama, M. Ino, 1983 .

Limitation of sputtered adhesion layer thickness for blanket CVD W in very high aspect contact filling

M. Yoshimaru, M. Ino, Shih-Chang Chen, 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

Effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride

M. Yoshimaru, M. Ino, H. Tamura, 1994 .

Rugged surface poly-Si electrode and low temperature deposited Si/sub 3/N/sub 4/ for 64 Mbit and beyond STC DRAM cell

M. Yoshimaru, M. Ino, Akihiro Sakamoto, 1990, International Technical Digest on Electron Devices.

A New Failure Mechanism And Its Improvement On Gate Oxide Reliability At Field Edge By Locos Isoiation

N. Hirashita, M. Takahashi, M. Ino, 1992 .

Silicon nitride thin-film deposition by LPCVD with in situ HF vapor cleaning and its application to stacked DRAM capacitor fabrication

M. Yoshimaru, M. Ino, N. Inoue, 1994 .