Larg Weiland

Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure

C. Hess, Larg Weiland, R. Bornefeld, 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

Digital tester-based measurement methodology for process control in multilevel metallization systems

Larg Weiland, Christopher Hess, 1995, Advanced Lithography.

Test time reduction methods for yield test structures

Larg Weiland, Christopher Hess, H. Read, 2003, International Conference on Microelectronic Test Structures, 2003..

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Larg Weiland, Christopher Hess, K. Sawada, 2002, Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..

Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure

Larg Weiland, Christopher Hess, Brian E. Stine, 2000, ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095).

Advanced Semiconductor Manufacturing Conference

Larg Weiland, Christopher Hess, C. Hess, 2002, ASMC 2002.

Defect cluster analysis to detect equipment-specific yield loss based on yield-to-area calculations

Larg Weiland, Christopher Hess, 1997, Advanced Lithography.

Addressable failure site test structures (AFS-TS) for CMOS processes: Design guidelines, fault simulation, and implementation

Ding-Ming Kwai, Charles Ching-Hsiang Hsu, Larg Weiland, 2001 .

Correlation between particle defects and electrical faults determined with laser scattering systems and digital measurements on checkerboard test structures

Larg Weiland, Christopher Hess, Guenter Lau, 1996, Advanced Lithography.

Passive Multiplexer Test Structure For Fast and Accurate Contact and Via Fail-Rate Evaluation

Larg Weiland, Christopher Hess, Brian E. Stine, 2001 .