Amrutha Iyer

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC

Pin-En Su, Bo Shen, Ichiro Fujimori, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 0.5–9.5-GHz, 1.2- $\mu \text{s}$ Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Pin-En Su, Bo Shen, Ichiro Fujimori, 2017, IEEE Journal of Solid-State Circuits.