Chiu-Wing Sham

发表

Design and error performance of punctured hadamard codes

Francis Chung-Ming Lau, Sheng Jiang, Wai M. Tam, 2017, 2017 23rd Asia-Pacific Conference on Communications (APCC).

A Novel Data Packing Technique for QC-LDPC Decoder Architecture applied to NAND flash controller

Longyu Ma, Chiu-Wing Sham, Hong-Fu Chou, 2019, 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE).

Operating frequency improvement on FPGA implementation of a pipeline large-FFT processor

Francis C. M. Lau, Chiu-Wing Sham, Ting-wai Siu, 2017, 2017 19th International Conference on Advanced Communication Technology (ICACT).

Hardware Design of Concatenated Zigzag Hadamard Encoder/Decoder System With High Throughput

Francis C. M. Lau, Chiu-Wing Sham, Sheng Jiang, 2020, IEEE Access.

Joint Shuffled Scheduling Decoding Algorithm for DP-LDPC Codes-Based JSCC Systems

Francis C. M. Lau, Lin Wang, Chiu-Wing Sham, 2019, IEEE Wireless Communications Letters.

Length matching in detailed routing for analog and mixed signal circuits

Qiang Gao, Yici Cai, Qiang Zhou, 2014, Microelectron. J..

Interconnect-driven floorplanning by searching alternative packings

Evangeline F. Y. Young, Hai Zhou, Chiu-Wing Sham, 2003, ASP-DAC '03.

A high throughput Gaussian noise generator

Francis Chung-Ming Lau, Qing Lu, Jianfeng Fan, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

SIAR: Customized real-time interactive router for analog circuits

Yici Cai, Qiang Zhou, Fan Yang, 2015, Integr..

A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes

Francis C. M. Lau, Qing Lu, Wai Man Tam, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard

Francis C. M. Lau, Qing Lu, Chiu-Wing Sham, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Congestion prediction in early stages

Evangeline F. Y. Young, Chiu-Wing Sham, 2005, SLIP '05.

A dual-MST approach for clock network synthesis

Evangeline F. Y. Young, Wing-Kai Chow, Chiu-Wing Sham, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Clock Network Synthesis with Concurrent Gate Insertion

Wing-Kai Chow, Chiu-Wing Sham, Jingwei Lu, 2010, PATMOS.

A Turbo-Hadamard Encoder/Decoder System with Hundreds of Mbps Throughput

Francis C. M. Lau, Kechao Huang, Sheng Jiang, 2018, 2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC).

Congestion prediction in floorplanning

Evangeline F. Y. Young, Chiu-Wing Sham, 2005, ASP-DAC.

A Visible Light Communication Based Integrated Circuit for Mobile Payment

Chiu-Wing Sham, Xinchao Zhong, 2019, 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE).

A parallel-routing network for reliability inferences of single-parity-check decoder

Francis C. M. Lau, Qing Lu, Chiu-Wing Sham, 2015, 2015 International Conference on Advanced Technologies for Communications (ATC).

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach

Liang Li, Wing-Kai Chow, Chiu-Wing Sham, 2014, Integr..

Routability driven floorplanner with buffer block planning

Evangeline F. Y. Young, Chiu-Wing Sham, 2002, ISPD '02.

A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

Xu Chen, Yue Zhao, Francis Chung-Ming Lau, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Fixed-Point Implementation of Convolutional Neural Networks for Image Classification

Francis C. M. Lau, Chiu-Wing Sham, Chun Y. Lo, 2018, 2018 International Conference on Advanced Technologies for Communications (ATC).

Energy Efficient Fixed-point Inference System of Convolutional Neural Network

Chiu-Wing Sham, Chun Yan Lo, Chiu-Wing Sham, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

A layered QC-LDPC decoder architecture for high speed communication system

Xu Chen, Yue Zhao, Francis Chung-Ming Lau, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes

Longyu Ma, Chiu-Wing Sham, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits

Hongxia Zhou, Hailong Yao, Chiu-Wing Sham, 2017, TODE.

A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems

Longyu Ma, Chiu-Wing Sham, Chun Yan Lo, 2020, 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE).

Raising the interest of students in engineering with an integrated summer programme

Kin-Man Lam, Siew-Chong Tan, Chiu-Wing Sham, 2012 .

An Ultimate-Shannon-Limit-Approaching Gbps Throughput Encoder/Decoder System

Chiu-Wing Sham, F. C. M. Lau, S. Jiang, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Routability-driven floorplanner with buffer block planning

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search

Chiu-Wing Sham, Jingwei Lu, 2013, International Symposium on Quality Electronic Design (ISQED).

An Optimization Approach for an RLL-Constrained LDPC Coded Recording System Using Deliberate Flipping

Chiu-Wing Sham, Hong-Fu Chou, 2018, IEEE Communications Letters.

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Wing-Kai Chow, Chiu-Wing Sham, Jingwei Lu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping

Chiu-Wing Sham, Hong-Fu Chou, 2017, 2017 International SoC Design Conference (ISOCC).

An architecture-algorithm co-design of artificial intelligence for Trax player

Francis C. M. Lau, Qing Lu, Chiu-Wing Sham, 2015, 2015 International Conference on Field Programmable Technology (FPT).

Area reduction by deadspace utilization on interconnect optimized floorplan

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2007, TODE.

Design of a high-throughput low-latency extended golay decoder

Francis Chung-Ming Lau, Chiu-Wing Sham, Pengwei Zhang, 2017, 2017 23rd Asia-Pacific Conference on Communications (APCC).

Optimal cell flipping in placement and floorplanning

Evangeline F. Y. Young, Chris C. N. Chu, Chiu-Wing Sham, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Tree-Permutation-Matrix Based LDPC Codes

Francis C. M. Lau, Sheng Jiang, Chiu-Wing Sham, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Block flipping and white space distribution for wirelength minimization

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2009, Integr..

Area reduction on interconnect optimized floorplan using deadspace utilization

Evangeline F. Y. Young, Chiu-Wing Sham, E.F.Y. Young, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Congestion estimation with buffer planning in floorplan design

Evangeline F. Y. Young, Chiu-Wing Sham, Wai-Chiu Wong, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A new clock network synthesizer for modern VLSI designs

Wing-Kai Chow, Chiu-Wing Sham, Jingwei Lu, 2012, Integr..

Slicing Floorplans with Handling Symmetry and General Placement Constraints

Hongxia Zhou, Hailong Yao, Chiu-Wing Sham, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Random-permutation-matrix-based cyclically-coupled LDPC codes

Francis C. M. Lau, Chiu-Wing Sham, Fanlu Mo, 2017, 2017 19th International Conference on Advanced Communication Technology (ICACT).

Using Neuroevolved Binary Neural Networks to solve reinforcement learning environments

Oliver Sinnen, Chiu-Wing Sham, Raul Valencia, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A bitstream reconfigurable FPGA implementation of the WSAT algorithm

Monk-Ping Leong, Philip Heng Wai Leong, Chiu-Wing Sham, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Area reduction by deadspace utilization on interconnect optimized floorplan

Evangeline F. Y. Young, Chiu-Wing Sham, 2007, TODE.

An SoC for Qi-compliant Wireless Power Transmitter With Enhanced EMI Performance

Chiu-Wing Sham, Xinchao Zhong, 2019, 2019 6th International Conference on Systems and Informatics (ICSAI).

Congestion prediction in early stages of physical design

Evangeline F. Y. Young, Chiu-Wing Sham, Jingwei Lu, 2009, TODE.

Efficient Decoding of QC-LDPC Codes Using GPUs

Xu Chen, Yue Zhao, Francis Chung-Ming Lau, 2011, ICA3PP.

On using the cyclically-coupled QC-LDPC codes in future SSDs

Francis C. M. Lau, Qing Lu, Chiu-Wing Sham, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Low-power reconfigurable acceleration of robust frequency-domain echo cancellation on FPGA

Chiu-Wing Sham, Wai-Chung Tang, C. H. Ho, 2010, The 2010 International Conference on Green Circuits and Systems.

Optimizing wirelength and routability by searching alternative packings in floorplanning

Evangeline F. Y. Young, Hai Zhou, Chiu-Wing Sham, 2008, TODE.

A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration

Longyu Ma, Chiu-Wing Sham, Jing Sun, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Congestion-oriented approach in placement for analog and mixed-signal circuits

Hongxia Zhou, Hailong Yao, Chiu-Wing Sham, 2013, Fifth Asia Symposium on Quality Electronic Design (ASQED 2013).

Novel types of cyclically-coupled quasi-cyclic LDPC block codes

Francis C. M. Lau, Qing Lu, Chiu-Wing Sham, 2016, 2016 International Conference on Advanced Technologies for Communications (ATC).

A Dynamically Reconfigurable QC-LDPC Implementation for Iris Recognition

Longyu Ma, Chiu-Wing Sham, Chun Yan Lo, 2021, 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE).

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes pdf

Longyu Ma, Chiu-Wing Sham, Xinchao Zhong, 2021, ArXiv.

Deep learning-based procedure for structural design of cold-formed steel channel sections with edge-stiffened and un-stiffened holes under axial compression

James B.P. Lim, Chiu-Wing Sham, Iman Hajirasouliha, 2021 .

Uncertainty-Aware Deep Co-training for Semi-supervised Medical Image Segmentation pdf

Jialei Chen, Chiu-Wing Sham, Chong Fu, 2021, Comput. Biol. Medicine.

Protograph-Based LDPC Hadamard Codes

Chiu-Wing Sham, Francis C. M. Lau, Peng-Wei Zhang, 2021, IEEE Transactions on Communications.

A More Compact Object Detector Head Network with Feature Enhancement and Relational Reasoning pdf

Chiu-Wing Sham, Xiang Li, Wen chao Zhang, 2021, Neurocomputing.

CNN Accelerator with Non-Blocking Network Design

Longyu Ma, Chiu-Wing Sham, Chun Yan Lo, 2021, 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE).

Deep learning-based axial capacity prediction for cold-formed steel channel sections using Deep Belief Network

James B.P. Lim, Chiu-Wing Sham, Krishanu Roy, 2021 .

A Highly Integrated RISC-V Based SoC for On-Board Unit in ETC System

Longyu Ma, Chiu-Wing Sham, Xinchao Zhong, 2021, 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE).

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

Longyu Ma, Chiu-Wing Sham, Chun Yan Lo, 2021, IEEE Access.