Thomas Eschbach

Orthogonal Hypergraph Drawing for Improved Visibility

Bernd Becker, Wolfgang Günther, Thomas Eschbach, 2006, J. Graph Algorithms Appl..

Orthogonal hypergraph routing for improved visibility

Bernd Becker, Wolfgang Günther, Thomas Eschbach, 2004, GLSVLSI '04.

Recursive bi-partitioning of netlists for large number of partitions

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface

Bernd Becker, Thomas Eschbach, Martina Welte, 2005, DeLFI Workshops.

GREEDY IIP: partitioning large graphs by greedy iterative improvement

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, 2001, Proceedings Euromicro Symposium on Digital Systems Design.

Cross Reduction for Orthogonal Circuit Visualization

Bernd Becker, Wolfgang Günther, Thomas Eschbach, 2003, VLSI.

Visualisierungen im Schaltkreisentwurf

Thomas Eschbach, 2008 .

Crossing Reduction by Windows Optimization

Rolf Drechsler, Bernd Becker, Wolfgang Günther, 2002, GD.

Recursive bi-partitioning of netlists for large number of partitions

Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, 2003, J. Syst. Archit..

Interactive circuit diagram visualization

Bernd Becker, Thomas Eschbach, B. Becker, 2008 .

Placement and routing optimization for circuits derived from BDDs

Rolf Drechsler, Bernd Becker, Thomas Eschbach, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Orthogonal circuit visualization improved by merging the placement and routing phases

Bernd Becker, Wolfgang Günther, Thomas Eschbach, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.