Bart Vanthournout

发表

An Overview of Open SystemC Initiative Standards Development

Trevor Wieman, Bishnupriya Bhattacharya, Tor E. Jeremiassen, 2012, IEEE Design & Test of Computers.

A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2005, Design, Automation and Test in Europe.

Jari Kreku, Kari Tiensyrjä, Bart Vanthournout, 2012 .

Synthesis of pipelined DSP accelerators with dynamic scheduling

Hugo De Man, Patrick Schaumont, Bart Vanthournout, 1995, Proceedings of the Eighth International Symposium on System Synthesis.

Task management in MPSoCs: An ASIP approach

Rainer Leupers, Gerd Ascheid, Torsten Kempf, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Synthesis of pipelined DSP accelerators with dynamic scheduling

Hugo De Man, Patrick Schaumont, Bart Vanthournout, 1997, IEEE Trans. Very Large Scale Integr. Syst..

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view

Rainer Leupers, Gerd Ascheid, Jeronimo Castrillon, 2010, 2010 International Symposium on System on Chip.

Synthesis of pipelined DSP accelerators with dynamic scheduling

Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, 1995 .

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis

Rainer Leupers, Gerd Ascheid, Han Zhang, 2011, Int. J. Embed. Real Time Commun. Syst..

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs

Rainer Leupers, Gerd Ascheid, Torsten Kempf, 2013, Int. J. Embed. Real Time Commun. Syst..

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

Axel Jantsch, Iraklis Anagnostopoulos, Philippe Martin, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

The MOSART Mapping Optimization for Multi-Core ARchiTectures

Axel Jantsch, Iraklis Anagnostopoulos, Philippe Martin, 2010, ISVLSI.

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Application-aware spinlock control using a hardware scheduler in MPSoC platforms

Rainer Leupers, Gerd Ascheid, Torsten Kempf, 2012, 2012 International Symposium on System on Chip (SoC).

System-Level Analysis of MPSoCs with a Hardware Scheduler

Rainer Leupers, Gerd Ascheid, Jeronimo Castrillon, 2014 .

High-Level Performance Estimation Using Simulators At Multiple Abstraction Levels

Geert Vanmeerbeeck, Bart Vanthournout, Prabhat Avasare, 2009 .

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach

Gerd Ascheid, Chantal Ykman-Couvreur, Giovanni Agosta, 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).