Miron Abramovici

发表

You can catch more bugs with transaction level honey

Kees G. W. Goossens, Adam Donlin, Miron Abramovici, 2008, CODES+ISSS '08.

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution

Mark Mohammad Tehranipoor, Michael S. Hsiao, James F. Plusquellic, 2013, IEEE Design & Test.

One-pass redundancy identification and removal

Miron Abramovici, Mahesh A. Iyer, 1992, Proceedings International Test Conference 1992.

Testing for Bridging Faults

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

Low-cost redundancy identification for combinational circuits

Miron Abramovici, Mahesh A. Iyer, 1994, Proceedings of 7th International Conference on VLSI Design.

Critical path tracing in sequential circuits

Premachandran R. Menon, Miron Abramovici, Ytzhak H. Levendel, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

FREEZE: a new approach for testing sequential circuits

Miron Abramovici, Krishna B. Rajan, David T. Miller, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Testing for Single Stuck Faults

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

MUST: multiple-stem analysis for identifying sequentially untestable faults

Qiang Peng, Jacob Savir, Miron Abramovici, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Dos and Don'ts in computing fault coverage

Miron Abramovici, 1993, Proceedings of IEEE International Test Conference - (ITC).

Selecting built-in self-test configurations for field programmable gate arrays

Charles E. Stroud, Miron Abramovici, Eric Lee, 1996, Conference Record. AUTOTESTCON '96.

Using embedded FPGAs for SoC yield improvement

Charles E. Stroud, Miron Abramovici, Marty Emmert, 2002, DAC '02.

We need more standards like IEEE 1500

Alfred L. Crouch, Miron Abramovici, 2009, IEEE Design & Test of Computers.

Online Fault Tolerance for FPGA Logic Blocks

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Global cost functions for test generation

Miron Abramovici, David T. Miller, R. Henning, 1990, Proceedings. International Test Conference 1990.

DIST-based detection and diagnosis of multiple faults in FPGAs

Charles E. Stroud, Miron Abramovici, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Critical Path Tracing - An Alternative to Fault Simulation

Premachandran R. Menon, P. R. Menon, Miron Abramovici, 1983, 20th Design Automation Conference Proceedings.

SCRIPT: a critical path tracing algorithm for synchronous sequential circuits

Premachandran R. Menon, Miron Abramovici, Ytzhak H. Levendel, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

BIST-based diagnosis of FPGA interconnect

Charles E. Stroud, Miron Abramovici, Jeremy Nall, 2002, Proceedings. International Test Conference.

What is the path to fast fault simulation?

John A. Waicukauski, Miron Abramovici, Bill Rogers, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Test Generation In Lamp2: System Overview

Premachandran R. Menon, Miron Abramovici, David T. Miller, 1985, ITC.

Critical Path Tracing: An Alternative to Fault Simulation

P. R. Menon, Miron Abramovici, D. T. Miller, 1984, IEEE Des. Test.

Using ILA testing for BIST in FPGAs

Charles E. Stroud, Miron Abramovici, Eric Lee, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

A SAT Solver Using Reconfigurable Hardware and Virtual Logic

José T. de Sousa, Miron Abramovici, M. Abramovici, 2000, Journal of Automated Reasoning.

On-Line Testing and Reconfiguration of Field Programmable Gate Arrays (FPGAs) for Fault-Tolerant (FT) Applications in Adaptive Computing Systems (ACS)

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2002 .

Dynamic redundancy identification in automatic test generation

Rabindra K. Roy, Miron Abramovici, David T. Miller, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Identifying sequentially untestable faults using illegal states

David E. Long, Miron Abramovici, Mahesh A. Iyer, 1995, Proceedings 13th IEEE VLSI Test Symposium.

BIST-Based Diaignostics of FPGA Logic Bllocks

Charles E. Stroud, Miron Abramovici, Eric Lee, 1997 .

Compact Test Generation Using a Frozen Clock Testing Strategy

Elizabeth M. Rudnick, Miron Abramovici, 2000, J. Inf. Sci. Eng..

The Best Flip-Flops to Scan

Rabindra K. Roy, Miron Abramovici, James J. Kulikowski, 1991, 1991, Proceedings. International Test Conference.

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

Ping Chen, Charles E. Stroud, Miron Abramovici, 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction

Melvin A. Breuer, Miron Abramovici, 1980, 17th Design Automation Conference.

Design for Testability

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

BIST-Based Delay-Fault Testing in FPGAs

Charles E. Stroud, Miron Abramovici, 2003, J. Electron. Test..

Sequentially untestable faults identified without search ("simple implications beat exhaustive search!")

Miron Abramovici, Mahesh A. Iyer, 1994, Proceedings., International Test Conference.

Increasing testability by clock transformation (getting rid of those darn states)

David E. Long, Miron Abramovici, Krishna B. Rajan, 1996, Proceedings of 14th VLSI Test Symposium.

Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, DFT.

A virtual logic algorithm for solving satisfiability problems using reconfigurable hardware

José T. de Sousa, Miron Abramovici, 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

Melvin A. Breuer, Miron Abramovici, M. Breuer, 1980, IEEE Transactions on Computers.

Surprises in sequential redundancy identification

David E. Long, Miron Abramovici, Mahesh A. Iyer, 1996, Proceedings ED&TC European Design and Test Conference.

BIST-Based Delay-Fault Testing in FPGAs

Charles E. Stroud, Miron Abramovici, C. Stroud, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

A logic simulation machine

P. R. Menon, Miron Abramovici, Y. H. Levendel, 1982, ISCA 1982.

BIST-based test and diagnosis of FPGA logic blocks

Charles E. Stroud, Miron Abramovici, C. Stroud, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Low-cost sequential ATPG with clock-control DFT

Elizabeth M. Rudnick, Xiaoming Yu, Miron Abramovici, 2002, DAC '02.

Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test

Sridhar Narayanan, Miron Abramovici, Sandeep Gupta, 2017, VTS.

At-speed logic BIST using a frozen clock testing strategy

Elizabeth M. Rudnick, Jongshin Shin, Miron Abramovici, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

On Redundancy and Fault Detection in Sequential Circuits

Melvin A. Breuer, Miron Abramovici, 1979, IEEE Transactions on Computers.

Checkpoint Faults are not Sufficient Target Faults for Test Generation

Premachandran R. Menon, Miron Abramovici, David T. Miller, 1986, IEEE Transactions on Computers.

In-system silicon validation using a reconfigurable platform

Miron Abramovici, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis

Melvin A. Breuer, Miron Abramovici, M. Breuer, 1982, IEEE Transactions on Computers.

System-level design verification in the AT&T computer division: overview and strategy

Miron Abramovici, R. G. Taylor, D. T. Miller, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Bridging pre-silicon verification and post-silicon validation

Alan J. Hu, Avi Ziv, Valeria Bertacco, 2010, Design Automation Conference.

Performance Penalty for Fault Tolerance in Roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2000, FPL.

A Logic Simulation Machine

Premachandran R. Menon, P. R. Menon, Miron Abramovici, 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A logic simulation machine

P. R. Menon, Miron Abramovici, Y. H. Levendel, 1982, ISCA.

A Configurable Hardware/Software Approach to SAT Solving

Joao Marques-Silva, José T. de Sousa, Miron Abramovici, 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

Dynamic fault tolerance in FPGAs via partial reconfiguration

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

Verification assertion dans des circuits integres

Miron Abramovici, 2005 .

Generating sequential test pattern with a prüfgerecht designed clock control

Miron Abramovici, Yu Champaign Xiaoming, 2002 .

A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Daniel G. Saab, José T. de Sousa, Miron Abramovici, 1999, DAC '99.

Sequential circuit ATPG using combinational algorithms

Xiaoming Yu, Miron Abramovici, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On combining design for testability techniques

Miron Abramovici, Prashant S. Parikh, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

(Finally, A Free Lunch: BIST Without Overhead!)

Charles E. Stroud, Miron Abramovici, Ping Chen, 1996 .

Dynamic redundancy identification in automatic test generation

Rabindra K. Roy, Miron Abramovici, David T. Miller, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Online BIST and BIST-based diagnosis of FPGA logic blocks

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Built-in self-test of FPGA interconnect

Charles E. Stroud, Miron Abramovici, Carter Hamilton, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

On-line BIST and diagnosis of FPGA interconnect using roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, Proceedings Seventh International On-Line Testing Workshop.

A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits

Miron Abramovici, 1982, IEEE Transactions on Computers.

FreezeFrame: compact test generation using a frozen clock strategy

Elizabeth M. Rudnick, Miron Abramovici, Matthew C. Merten, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

BIST-based diagnostics of FPGA logic blocks

Charles E. Stroud, Miron Abramovici, Eric Lee, 1997, Proceedings International Test Conference 1997.

Digital Systems Testing & Testable Design

Melvin A. Breuer, Miron Abramovici, Allan D. Friedman, 1993 .

Concurrent fault simulation and functional level modeling

Melvin A. Breuer, Miron Abramovici, K. Kumar, 1977, DAC '77.

Low-Cost Fault Simulation: Why, When and How

Miron Abramovici, 1985, ITC.

Satisfiability on reconfigurable hardware

Daniel G. Saab, Miron Abramovici, D. Saab, 1997, FPL.

A Cost-Based Approach to Partial Scan

Miron Abramovici, Prashant S. Parikh, 1993, 30th ACM/IEEE Design Automation Conference.

Digital Systems Testing and Design for Testability

Melvin A. Breuer, Miron Abramovici, Allan D. Friedman, 1990 .

Identifying sequential redundancies without search

David E. Long, Miron Abramovici, Mahesh A. Iyer, 1996, DAC '96.

Testability-based partial scan analysis

Miron Abramovici, Prashant S. Parikh, M. Abramovici, 1995, J. Electron. Test..

Test Generation In Lamp2: Concepts and Algorithms

Premachandran R. Menon, Miron Abramovici, David T. Miller, 1985, ITC.

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults

Premachandran R. Menon, P. R. Menon, Miron Abramovici, 1985, IEEE Transactions on Computers.

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults

David E. Long, Miron Abramovici, Mahesh A. Iyer, 2000, TODE.

On selecting flip-flops for partial reset

Daniel G. Saab, Miron Abramovici, Ben Mathew, 1993, Proceedings of IEEE International Test Conference - (ITC).

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

Charles E. Stroud, Miron Abramovici, Vinay Verma, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

WARNING: 100% Fault Coverage May Be Misleading!!

Miron Abramovici, Prashant S. Parikh, 1992, Proceedings International Test Conference 1992.

Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

Ping Chen, Charles E. Stroud, Miron Abramovici, 1996, Proceedings of 14th VLSI Test Symposium.

A reconfigurable design-for-debug infrastructure for SoCs

Gérard Memmi, Miron Abramovici, Paul Bradley, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Fault simulation on reconfigurable hardware

Miron Abramovici, P. Menon, 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

A Maximal Resolution Guided-Probe Testing Algorithm

Miron Abramovici, 1981, 18th Design Automation Conference.

Digital systems testing and testable design

Melvin A. Breuer, Arthur D. Friedman, A. D. Friedman, 1990 .

Integrated circuit security: new threats and solutions

Miron Abramovici, Paul Bradley, M. Abramovici, 2009, CSIIRW '09.

System-level design verification in the AT&T Computer Division: tools

P. R. Menon, Miron Abramovici, D. T. Miller, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

In-System Silicon Validation and Debug

Miron Abramovici, M. Abramovici, 2008, IEEE Design & Test of Computers.

Built-In Self-Test of Logic Blocks in FPGAs

Charles E. Stroud, Ping Chen, Miron Abramovici, 2000 .

FIRE: a fault-independent combinational redundancy identification algorithm

Miron Abramovici, Mahesh A. Iyer, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Sequential ATPG Using Combinational Algorithms

Miron Abramovici, Xiaoming Yu, Elizabeth Rudnick, .