C. Lee

Flip chip solder joint reliability analysis using viscoplastic and elastic-plastic-creep constitutive models

A. Yeo, J.H.L. Pang, C. Lee, 2006, IEEE Transactions on Components and Packaging Technologies.

Metrology for characterization of wafer thickness uniformity during 3DS-IC processing

C. Lee, C. Lee, A. Shorey, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Overview and Emerging Challenges in Wafer Thinning Process for Handheld Applications

V.P. Ganesh, C. Lee, 2006, 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium.

Process and Material Characterization of Die Attach Film (DAF) for Thin Die Applications

C. Lee, M. Teo, Soh Choew Kheng, 2006, 2006 International Conference on Electronic Materials and Packaging.

Flip chip solder joint fatigue life model investigation

A. Yeo, John H. L. Pang, C. Lee, 2002, 4th Electronics Packaging Technology Conference, 2002..

Influence of bump geometry, adhesives and pad finishings on the joint resistance of Au bump and A/NCA flip chip interconnection

A. Yeo, C. Lee, Tan Ai Min, 2005, 2005 7th Electronic Packaging Technology Conference.

Application of finite element analysis on flip chip ball grid array package with 65nm Cu/low-κ device

A. Yeo, C. Lee, C. Lee, 2006, 2006 8th Electronics Packaging Technology Conference.

Flip Chip Interconnection Systems and its Reliability Performance

A. Yeo, C. Lee, C. Lee, 2006, 2006 1st Electronic Systemintegration Technology Conference.

Reliability assessment of flipchip on build up laminate based multi-chip package

D. Pinjala, T. C. Chai, C. Lee, 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

SAM interpretation of interfacial anomaly in flip-chip BGA package with 65 nm Cu/low-κ integrated circuits device

P. Lee, C. Lee, Ka Yau Lee, 2006, 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium.

Flip chip solder joint fatigue analysis using 2D and 3D FE models

A. Yeo, C. Lee, J. Pang, 2004, 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the.

Package optimization of a stacked die flip chip based test package

K. Pressel, C. Lee, G. Ofner, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

A new leadframe design solution for improved pop-corn cracking performance

H. Pape, C. Lee, C. Lee, 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.