Luigi Dilillo

发表

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2012, J. Electron. Test..

Power-Aware Test Pattern Generation for At-Speed LOS Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

Luigi Dilillo, Emna Farjallah, Jean-Marc Armani, 2019, Microelectronics Reliability.

An effective hybrid fault-tolerant architecture for pipelined cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 20th IEEE European Test Symposium (ETS).

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme

Alberto Bosio, Luigi Dilillo, Kohei Miyase, 2011 .

Comparison of open and resistive-open defect test conditions in SRAM address decoders

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2003, 2003 Test Symposium.

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

Evaluation of test algorithms stress effect on SRAMs under neutron radiation

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

On using a SPICE-like TSTAC™ eFlash model for design and test

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Intra-Cell Defects Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

A study of path delay variations in the presence of uncorrelated power and ground supply noise

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Versatile march test generator for hands-on memory testing laboratory

Luigi Dilillo, Jean Marc Gallière, 2011, 2011 IEEE International Conference on Microelectronic Systems Education.

Data retention fault in SRAM memories: analysis and detection procedures

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Enabling deep-space CubeSat missions through state-of-the-art radiation-hardened technologies

Luigi Dilillo, Leonardo Kessler Slongo, Laio Oriel Seman, 2018 .

Fault Localization Improvement Through an Intra-Cell Diagnosis Approach

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems

Alberto Bosio, Luigi Dilillo, Helmut Puchner, 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Design-for-Diagnosis Architecture for Power Switches

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

March iC-: an improved version of March C- for ADOFs detection

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

NAND flash testing: A preliminary study on actual defects

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2009, 2009 International Test Conference.

Failure Analysis and Test Solutions for Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs

Arnaud Virazel, Luigi Dilillo, Christian Landrault, 2008 .

Globally Constrained Locally Optimized 3-D Power Delivery Networks

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Resistive-Open Defects in Pre-charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2010 .

A roaming memory test bench for detecting particle induced SEUs

Luigi Dilillo, Patrick Girard, Jean Marc Gallière, 2010, 2010 IEEE International Test Conference.

Resistive-Open Defects in Sense Amplifiers

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2010 .

Advanced test methods for SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2008, 2008 IEEE International Test Conference.

Pre-flight qualification test procedure for nanosatellites using sounding rockets

Luigi Dilillo, Leonardo Kessler Slongo, Eduardo Augusto Bezerra, 2019 .

Test and Reliability of Magnetic Random Access Memories

João Azevedo, Arnaud Virazel, Luigi Dilillo, 2012 .

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Impact of Resistive-Bridging Defects in SRAM Core-Cell

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Computing detection probability of delay defects in signal line tsvs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 18th IEEE European Test Symposium (ETS).

Dynamic Mode Testing of SRAMS under Neutron Radiation

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2010, 2010 15th IEEE European Test Symposium.

Comprehensive bridging fault diagnosis based on the SLAT paradigm

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On using address scrambling to implement defect tolerance in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 IEEE International Test Conference.

Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2013 .

Test solution for data retention faults in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Basics on SRAM Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

iBoX — Jitter based Power Supply Noise sensor

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 19th IEEE European Test Symposium (ETS).

An effective BIST architecture for power-gating mechanisms in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

A Comprehensive System-on-Chip Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, J. Electron. Test..

On the Generation of Diagnostic Test Set for Intra-cell Defects

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 23rd Asian Test Symposium.

A calculation method to estimate single event upset cross section

Luigi Dilillo, Antoine D. Touboul, Frédéric Saigné, 2017, Microelectron. Reliab..

SoC Yield Improvement for Future Nanoscale Technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, ETS 2009.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics

Luigi Dilillo, Emna Farjallah, Jean-Marc Armani, 2017, 2017 IEEE International Test Conference (ITC).

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

Resistive-open defects in embedded-SRAM core cells: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 13th Asian Test Symposium.

Mapping Test Power to Functional Power through Smart X-Filling for LOS Scheme

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011 .

Effect-cause intra-cell diagnosis at transistor level

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, International Symposium on Quality Electronic Design (ISQED).

Soft errors in commercial off-the-shelf static random access memories

Luigi Dilillo, Georgios Tsiligiannis, Alexandre Louis Bosser, 2017 .

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 IEEE International Test Conference (ITC).

Resistive-Open Defects in Address Decoders

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Diagnosis and Design-for-Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Reducing Power Dissipation in SRAM during Test

Luigi Dilillo, Patrick Girard, Bashir M. Al-Hashimi, 2006, J. Low Power Electron..

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Low-power SRAMs power mode control logic: Failure analysis and test solutions

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE International Test Conference.

Through-Silicon-Via resistive-open defect analysis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

Electro-Thermal Analysis of 3D Power Delivery Networks

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, DAC 2012.

Faults Due to Process Variations in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Why and How Controlling Power Consumption during Test: A Survey

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 21st Asian Test Symposium.

Methodologies for the Statistical Analysis of Memory Response to Radiation

Ari Virtanen, Luigi Dilillo, Helmut Puchner, 2016, IEEE Transactions on Nuclear Science.

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2008 .

SRAM testing under Neutron Radiation for the evaluation of different algorithms stress

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

Peak Power Estimation: A Case Study on CPU Cores

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2012, 2012 IEEE 21st Asian Test Symposium.

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes

Mark Mohammad Tehranipoor, Xiaoqing Wen, Arnaud Virazel, 2010, J. Low Power Electron..

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 22nd Asian Test Symposium.

Efficient Test of Dynamic Read Destructive Faults in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005 .

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2013, J. Low Power Electron..

Timing-aware ATPG for critical paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Complete Framework for the Estimation of the SRAM Core-Cell Resilience to Radiation

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2012 .

A new design-for-test technique for SRAM core-cell stability faults

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Impact of resistive-open defects on the heat current of TAS-MRAM architectures

Luigi Dilillo, Aida Todri, Alberto Bosio, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Defect analysis in power mode control logic of low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année

Giorgio Di Natale, Arnaud Virazel, Alberto Bosio, 2010 .

Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design †

Luigi Dilillo, Douglas R Melo, Cesar A Zeferino, 2019, Sensors.

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories

Luigi Dilillo, Bashir M. Al-Hashimi, B. Al-Hashimi, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Robust data collection and transfer framework for a distributed SRAM based neutron sensor

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2011, 2011 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI).

An Error Resilient Platform for Data Transfer and Power Management for a Distributed SRAM-based Neutron Detection Test Bench

Luigi Dilillo, 2012 .

An intra-cell defect grading tool

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2009 .

Coupling-based resistive-open defects in TAS-MRAM architectures

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

SRAM Core-cell Quality Metrics

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Power Supply Noise Sensor Based on Timing Uncertainty Measurements

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 21st Asian Test Symposium.

Scan-chain intra-cell defects grading

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A Logic Diagnosis Approach for Sequential Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, ETS 2009.

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps

Luigi Dilillo, Emna Farjallah, Jean-Marc Armani, 2017, 2017 22nd IEEE European Test Symposium (ETS).

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes

Wei Zhao, Mark Mohammad Tehranipoor, Xiaoqing Wen, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

Exploring the impact of functional test programs re-used for power-aware testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011, 2011 Asian Test Symposium.

Test and diagnosis of power switches

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Is test power reduction through X-filling good enough?

Mark Mohammad Tehranipoor, Xiaoqing Wen, Arnaud Virazel, 2010, 2010 IEEE International Test Conference.

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2007, J. Electron. Test..

Delay Fault Diagnosis in Sequential Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, 2009 Asian Test Symposium.

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, European Test Symposium (ETS'05).

Implementation of fault tolerance techniques for integrated network interfaces

Luigi Dilillo, Eduardo Augusto Bezerra, Douglas Rossi de Melo, 2018 .

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

Luigi Dilillo, Bashir M. Al-Hashimi, Patrick Girard, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Resistive-Open Defects in Core-Cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Resistive-Open Defects in Write Drivers

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems

Luigi Dilillo, Cesar Albenes Zeferino, Lucas Matana Luza, 2020, 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Parity prediction synthesis for nano-electronic gate designs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 IEEE International Test Conference.

Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells

Luigi Dilillo, Emna Farjallah, Jean-Marc Armani, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM

Alberto Bosio, Luigi Dilillo, Helmut Puchner, 2020, 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant Architecture

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

Design for Test and Diagnosis of Power Switches

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2016, J. Circuits Syst. Comput..

Setting test conditions for improving SRAM reliability

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.

An effective ATPG flow for Gate Delay Faults

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 18th IEEE European Test Symposium (ETS).

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, J. Electron. Test..

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

A Comprehensive Evaluation of Functional Programs for Power-Aware Test

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 23rd North Atlantic Test Workshop.

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router

Luigi Dilillo, Eduardo Augusto Bezerra, Douglas Rossi de Melo, 2019, 2019 IEEE Latin American Test Symposium (LATS).

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2004 .

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Detecting NBTI induced failures in SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 28th VLSI Test Symposium (VTS).

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Sixteenth IEEE European Test Symposium.

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, IEEE Transactions on Electron Devices.

Interconnection Architecture for Dependable Multicore Systems

Luigi Dilillo, Eduardo Augusto Bezerra, Douglas Rossi de Melo, 2018 .

A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites

Luigi Dilillo, Leonardo Kessler Slongo, Laio Oriel Seman, 2019, 2019 IEEE Latin American Test Symposium (LATS).

A Model-Based Framework to Assess the Reliability of Safety-Critical Applications

Alberto Bosio, Luigi Dilillo, Lucas Matana Luza, 2021, 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks

Alberto Bosio, Luigi Dilillo, Annachiara Ruospo, 2021, 2021 IEEE 22nd Latin American Test Symposium (LATS).

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router

Luigi Dilillo, Eduardo Augusto Bezerra, Cesar Albenes Zeferino, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study

Luigi Dilillo, Christian Poivey, Maria Kastriotou, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Characterization of a RISC-V System-on-Chip under Neutron Radiation

Luigi Dilillo, Maria Kastriotou, Cesar A. Zeferino, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Proton-Induced Single-Event Degradation in SDRAMs

Luigi Dilillo, Robert Ecoffet, Frederic Wrobel, 2016, IEEE Transactions on Nuclear Science.

Heavy-Ion Radiation Impact on a 4 Mb FRAM Under Different Test Modes and Conditions

Ari Virtanen, Luigi Dilillo, Helmut Puchner, 2016, IEEE Transactions on Nuclear Science.

Neutron-Induced Failure in Silicon IGBTs, Silicon Super-Junction and SiC MOSFETs

Luigi Dilillo, Dimitri Linten, Eddy Simoen, 2012, IEEE Transactions on Nuclear Science.

Neutron-induced failure in super-junction, IGBT, and SiC power devices

Luigi Dilillo, Dimitri Linten, Eddy Simoen, 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

Neutron detection through an SRAM-based test bench

Luigi Dilillo, Frederic Wrobel, Frederic Saigne, 2009, 2009 3rd International Workshop on Advances in sensors and Interfaces.

Soft Error Triggering Criterion Based on Simplified Electrical Model of the SRAM Cell

Luigi Dilillo, F. Saigne, Antoine D. Touboul, 2013, IEEE Transactions on Nuclear Science.

Temperature Impact on the Neutron SER of a Commercial 90nm SRAM

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013 .

Analysis of Resistive-Open Defects in TAS-MRAM Array

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, ITC 2011.

Evaluating a radiation monitor for mixed-field environments based on SRAM technology

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014 .

A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to Neutrons

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .