Patrick Girard

发表

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2012, J. Electron. Test..

Hardware Generation of Random Single Input Change Test Sequences

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, J. Electron. Test..

Power-Aware Test Pattern Generation for At-Speed LOS Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Robin Wilson, Arnaud Virazel, Alberto Bosio, 2015, Sixteenth International Symposium on Quality Electronic Design.

Is aproximate computing suitable for selective hardening of arithmetic circuits?

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

An effective hybrid fault-tolerant architecture for pipelined cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 20th IEEE European Test Symposium (ETS).

Survey of low-power testing of VLSI circuits

Patrick Girard, 2002, IEEE Design & Test of Computers.

Comparison of open and resistive-open defect test conditions in SRAM address decoders

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2003, 2003 Test Symposium.

A novel method to mitigate TSV electromigration for 3D ICs

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A gated clock scheme for low power scan-based BIST

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2001, Proceedings Seventh International On-Line Testing Workshop.

Power-aware test generation with guaranteed launch safety for at-speed scan testing

Mark Mohammad Tehranipoor, Xiaoqing Wen, Patrick Girard, 2011, 29th VLSI Test Symposium.

An adjacency-based test pattern generator for low power BIST design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2000, Proceedings of the Ninth Asian Test Symposium.

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Patrick Girard, Zhengfeng Huang, Jun Zhou, 2019, IEEE Access.

An implicit delay fault simulation method with approximate detection threshold calculation

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1993, Proceedings of IEEE International Test Conference - (ITC).

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

A Design-for-Diagnosis Technique for SRAM Write Drivers

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, 2008 Design, Automation and Test in Europe.

A gate resizing technique for high reduction in power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Guest Editorial

Patrick Girard, Nicola Nicolici, 2008, J. Electron. Test..

A new absorption based model for sheet reheat in thermoforming

Patrick Girard, Benoit Boulet, Benoit Boulet, 2005 .

A trace-based method for delay fault diagnosis in synchronous sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Evaluation of test algorithms stress effect on SRAMs under neutron radiation

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

On using a SPICE-like TSTAC™ eFlash model for design and test

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Intra-Cell Defects Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

A study of path delay variations in the presence of uncorrelated power and ground supply noise

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Power-Driven Routing-Constrained Scan Chain Design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2004, J. Electron. Test..

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2006, J. Electron. Test..

Hidden Markov and independence models with patterns for sequential BIST

Patrick Girard, Christian Landrault, Olivier Gascuel, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Data retention fault in SRAM memories: analysis and detection procedures

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Is triple modular redundancy suitable for yield improvement?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009, IET Comput. Digit. Tech..

Fault Localization Improvement Through an Intra-Cell Diagnosis Approach

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Design-for-Diagnosis Architecture for Power Switches

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

March iC-: an improved version of March C- for ADOFs detection

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

NAND flash testing: A preliminary study on actual defects

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2009, 2009 International Test Conference.

Failure Analysis and Test Solutions for Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

Analysis of Resistive-Open Defects in SRAM Sense Amplifiers

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low power testing of VLSI circuits: problems and solutions

Patrick Girard, P. Girard, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Globally Constrained Locally Optimized 3-D Power Delivery Networks

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Resistive-Open Defects in Pre-charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2010 .

A roaming memory test bench for detecting particle induced SEUs

Luigi Dilillo, Patrick Girard, Jean Marc Gallière, 2010, 2010 IEEE International Test Conference.

Resistive-Open Defects in Sense Amplifiers

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2010 .

A New Reliable Method for Delay-Fault Diagnosis

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, The Fifth International Conference on VLSI Design.

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

Mark Mohammad Tehranipoor, Xiaoqing Wen, Patrick Girard, 2010, IEICE Trans. Inf. Syst..

Design of routing-constrained low power scan chains

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Advanced test methods for SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2008, 2008 IEEE International Test Conference.

Test and Reliability of Magnetic Random Access Memories

João Azevedo, Arnaud Virazel, Luigi Dilillo, 2012 .

SoC Yield Improvement: Redundant Architectures to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Test Conference.

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, J. Low Power Electron..

Impact of Resistive-Bridging Defects in SRAM Core-Cell

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2001, J. Electron. Test..

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Approximate computing: Design & test for integrated circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 18th IEEE Latin American Test Symposium (LATS).

BIST of delay faults in the logic architecture of symmetrical FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications

Patrick Girard, Hassen Aziza, Pablo Ilha Vaz, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Towards approximation during test of Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Test power: a big issue in large SOC designs

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

A Mixed Approach for Unified Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM

Patrick Girard, Panagiota Papavramidou, Michael Nicolaidis, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Dynamic Mode Testing of SRAMS under Neutron Radiation

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, 2010, 2010 15th IEEE European Test Symposium.

Defect analysis for delay-fault BIST in FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Comprehensive bridging fault diagnosis based on the SLAT paradigm

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On using address scrambling to implement defect tolerance in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 IEEE International Test Conference.

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications

Patrick Girard, Zhili Chen, Zhen Wu, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Power driven chaining of flip-flops in scan architectures

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2002, Proceedings. International Test Conference.

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric

Mark Mohammad Tehranipoor, Patrick Girard, Junxia Ma, 2010, GLSVLSI '10.

Delay fault diagnosis in sequential circuits based on path tracing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Integr..

DFSIM: a gate-delay fault simulator for sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings ED&TC European Design and Test Conference.

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Patrick Girard, Yannick Bonhomme, P. Girard, 2005, Journal of Low Power Electronics.

Test solution for data retention faults in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Basics on SRAM Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Is TMR Suitable for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009 .

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A diagnostic ATPG for delay faults based on genetic algorithms

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

iBoX — Jitter based Power Supply Noise sensor

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 19th IEEE European Test Symposium (ETS).

An effective BIST architecture for power-gating mechanisms in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

A Comprehensive System-on-Chip Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, J. Electron. Test..

A Gated Clock Scheme for Low Power Testing of Logic Cores

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, J. Electron. Test..

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

On the Generation of Diagnostic Test Set for Intra-cell Defects

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 23rd Asian Test Symposium.

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

Patrick Girard, Jun Zhou, Zhen Wu, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

SoC Yield Improvement for Future Nanoscale Technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, ETS 2009.

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

High quality TPG for delay faults in look-up tables of FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Patrick Girard, Xiaoqing Wen, Aibin Yan, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

A novel approach to delay-fault diagnosis

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Resistive-open defects in embedded-SRAM core cells: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 13th Asian Test Symposium.

Mapping Test Power to Functional Power through Smart X-Filling for LOS Scheme

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011 .

On using machine learning for logic BIST

Patrick Girard, Christian Landrault, Christophe Fagot, 1997, Proceedings International Test Conference 1997.

Effect-cause intra-cell diagnosis at transistor level

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, International Symposium on Quality Electronic Design (ISQED).

A History-Based Technique for Faults Diagnosis in SRAMs

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008 .

SoC Symbolic Simulation: a case study on delay fault testing

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Yield Improvement, Fault-Tolerance to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Delay-fault diagnosis by critical-path tracing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, IEEE Design & Test of Computers.

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Arnaud Virazel, Patrick Girard, Pankaj Agarwal, 2016, J. Electron. Test..

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 IEEE International Test Conference (ITC).

Resistive-Open Defects in Address Decoders

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Diagnosis and Design-for-Diagnosis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Reducing Power Dissipation in SRAM during Test

Luigi Dilillo, Patrick Girard, Bashir M. Al-Hashimi, 2006, J. Low Power Electron..

Low power BIST design by hypergraph partitioning: methodology and architectures

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Circuit partitioning for low power BIST design with minimized peak power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

An overview of failure mechanisms in embedded flash memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 24th IEEE VLSI Test Symposium.

A hybrid power modeling approach to enhance high-level power models

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Resistive-Open Defects in core cells: Analysis and March Test Solution *

Arnaud Virazel, Patrick Girard, Simone Borri, 2004 .

Low-power SRAMs power mode control logic: Failure analysis and test solutions

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE International Test Conference.

Through-Silicon-Via resistive-open defect analysis

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

High Defect Coverage with Low-Power Test Sequences in a BIST Environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, IEEE Des. Test Comput..

Faults Due to Process Variations in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

On using efficient test sequences for BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Auto-adaptive ultra-low power IC

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

Why and How Controlling Power Consumption during Test: A Survey

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 21st Asian Test Symposium.

SRAM testing under Neutron Radiation for the evaluation of different algorithms stress

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

A test vector inhibiting technique for low energy BIST design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Peak Power Estimation: A Case Study on CPU Cores

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2012, 2012 IEEE 21st Asian Test Symposium.

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes

Mark Mohammad Tehranipoor, Xiaoqing Wen, Arnaud Virazel, 2010, J. Low Power Electron..

Maximizing Yield for Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis

Patrick Girard, P. Rosinger, Luigi Dilillo, 2006 .

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Mark Mohammad Tehranipoor, Patrick Girard, Junxia Ma, 2012, J. Electron. Test..

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 22nd Asian Test Symposium.

Evaluation of currents in the fA range

Patrick Girard, P. Nouet, 1990 .

An effective approach for functional test programs compaction

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2013, J. Low Power Electron..

A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics

Patrick Girard, 2018, J. Low Power Electron..

An efficient scan tree design for test time reduction

Patrick Girard, Hideo Fujiwara, Tomokazu Yoneda, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Timing-aware ATPG for critical paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

An optimized BIST test pattern generator for delay testing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

A new design-for-test technique for SRAM core-cell stability faults

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Defect analysis in power mode control logic of low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

An Exact and Efficient Critical Path Tracing Algorithm

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

A ring architecture strategy for BIST test pattern generation

Patrick Girard, Christian Landrault, Olivier Gascuel, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Testing approximate digital circuits: Challenges and opportunities

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

Improving Diagnosis Resolution without Physical Information

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, J. Electron. Test..

Robust data collection and transfer framework for a distributed SRAM based neutron sensor

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2011, 2011 4th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI).

Variability Analysis of an SRAM Test Chip

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2011, ETS 2011.

On pinpoint capture power management in at-speed scan test generation

Mark Mohammad Tehranipoor, Xiaoqing Wen, Patrick Girard, 2012, 2012 IEEE International Test Conference.

An intra-cell defect grading tool

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Case Study on Logic Diagnosis for Industrial Circuits

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, 2008 .

A Special Section on New and Future Trends in Low Power Electronics

Patrick Girard, 2017, J. Low Power Electron..

DERRIC: A Tool for Unified Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2007, 12th IEEE European Test Symposium (ETS'07).

A Ring Architecture Strategy for BIST Test Pattern Generation

Patrick Girard, Christian Landrault, Olivier Gascuel, 2003, J. Electron. Test..

Power-Aware Testing and Test Strategies for Low Power Devices

Kaushik Roy, Xiaoqing Wen, Patrick Girard, 2008, 2008 Design, Automation and Test in Europe.

Random Adjacent Sequences: An Efficient Solution for Logic BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2001, VLSI-SOC.

Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2009 .

Test of low power circuits: Issues and industrial practices

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

SRAM Core-cell Quality Metrics

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Power Supply Noise Sensor Based on Timing Uncertainty Measurements

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 21st Asian Test Symposium.

Scan-chain intra-cell defects grading

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Xiaoqing Wen, Patrick Girard, Kohei Miyase, 2007, 2007 IEEE International Test Conference.

A Logic Diagnosis Approach for Sequential Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, ETS 2009.

Low Power BIST by Filtering Non-Detecting Vectors

João Paulo Teixeira, Patrick Girard, Serge Pravossoudovitch, 1999, European Test Workshop 1999 (Cat. No.PR00390).

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

An advanced diagnostic method for delay faults in combinational faulty circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, J. Electron. Test..

A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2010, IEEE Transactions on Computers.

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache

Patrick Girard, Xiaochen Guo, Keren Liu, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes

Wei Zhao, Mark Mohammad Tehranipoor, Xiaoqing Wen, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Welcome to the Journal of Low Power Electronics

Patrick Girard, 2005, J. Low Power Electron..

A non-iterative gate resizing algorithm for high reduction in power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Integr..

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2009, J. Electron. Test..

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 1999, J. Electron. Test..

Exploring the impact of functional test programs re-used for power-aware testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient scan chain design for power minimization during scan testing under routing constraint

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

An effective fault-injection framework for memory reliability enhancement perspectives

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011, 2011 Asian Test Symposium.

Test and diagnosis of power switches

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Is test power reduction through X-filling good enough?

Mark Mohammad Tehranipoor, Xiaoqing Wen, Arnaud Virazel, 2010, 2010 IEEE International Test Conference.

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2007, J. Electron. Test..

Delay Fault Diagnosis in Sequential Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009, 2009 Asian Test Symposium.

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, J. Electron. Test..

Scan-Chain Intra-Cell Aware Testing

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, IEEE Transactions on Emerging Topics in Computing.

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, European Test Symposium (ETS'05).

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs

Jie Song, Patrick Girard, Zhengfeng Huang, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Mitigate TSV Electromigration for 3D ICs - From the Architecture Perspective

Alberto Bosio, Patrick Girard, Pascal Vivet, 2013 .

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Resistive-Open Defects in Core-Cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

A new test pattern generation method for delay fault testing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings of 14th VLSI Test Symposium.

Diagnostic of path and gate delay faults in non-scan sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Proceedings 13th IEEE VLSI Test Symposium.

A modified clock scheme for a low power BIST test pattern generator

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

A case study on logic diagnosis for System-on-Chip

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009, 2009 10th International Symposium on Quality Electronic Design.

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Parity prediction synthesis for nano-electronic gate designs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 IEEE International Test Conference.

An efficient fault simulation technique for transition faults in non-scan sequential circuits

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant Architecture

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

Setting test conditions for improving SRAM reliability

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.

Radiation Induced Effects on Electronic Systems and ICs

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2012 .

An effective ATPG flow for Gate Delay Faults

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 18th IEEE European Test Symposium (ETS).

A BIST structure to test delay faults in a scan environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

Mark Mohammad Tehranipoor, Xiaoqing Wen, Patrick Girard, 2008, 2008 17th Asian Test Symposium.

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, J. Electron. Test..

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Towards digital circuit approximation by exploiting fault simulation

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 IEEE East-West Design & Test Symposium (EWDTS).

A test vector ordering technique for switching activity reduction during test operation

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Microprocessor Testing: Functional Meets Structural Test

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, J. Circuits Syst. Comput..

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns

Wei Zhao, Mark Mohammad Tehranipoor, Xiaoqing Wen, 2012, J. Low Power Electron..

Using TMR Architectures for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Detecting NBTI induced failures in SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 28th VLSI Test Symposium (VTS).

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Patrick Girard, Jun Zhou, Tianming Ni, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Sixteenth IEEE European Test Symposium.

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2005, J. Electron. Test..

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron Radiation

Arnaud Virazel, Patrick Girard, Alberto Bosio, 2012 .

Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, IEEE Transactions on Electron Devices.

Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata

Patrick Girard, Ambika Prasad Shah, Michael Waltl, 2021, 2021 IEEE European Test Symposium (ETS).

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

Arnaud Virazel, Patrick Girard, Said Hamdioui, 2021, Electronics.

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Arnaud Virazel, Patrick Girard, Hassen Aziza, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Xiaoqing Wen, Patrick Girard, Zhengfeng Huang, 2021, Microelectron. J..

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

Patrick Girard, Xiaochen Guo, Yuanqing Cheng, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Patrick Girard, Tianming Ni, Aibin Yan, 2021, J. Electron. Test..

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing

Arnaud Virazel, Patrick Girard, Bastien Deveautour, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*

Jürgen Teich, Muhammad Abdullah Hanif, Arnaud Virazel, 2021, 2021 IEEE European Test Symposium (ETS).

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Arnaud Virazel, Patrick Girard, Matteo Sonza Reorda, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments

Xiaoqing Wen, Patrick Girard, Tianming Ni, 2021, ACM Great Lakes Symposium on VLSI.

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Patrick Girard, Santosh Kumar Vishvakarma, Ambika Prasad Shah, 2021, Electronics.

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Patrick Girard, Santosh Kumar Vishvakarma, Ambika Prasad Shah, 2021, ACM Great Lakes Symposium on VLSI.

A Learning-Based Methodology for Accelerating Cell-Aware Model Generation

Arnaud Virazel, Patrick Girard, Aymen Ladhar, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006)

Patrick Girard, Mohamed Masmoudi, Michel Renovell, 2006 .

Temperature Impact on the Neutron SER of a Commercial 90nm SRAM

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013 .

Analysis of Resistive-Open Defects in TAS-MRAM Array

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, ITC 2011.

Evaluating a radiation monitor for mixed-field environments based on SRAM technology

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014 .

A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to Neutrons

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .