Kazuyuki Miyazawa

A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

Katsutaka Kimura, Katsuhiro Shimohigashi, Shinji Shimizu, 1987 .

High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Toshio Maeda, 1992 .

A 17ns 4Mb BICMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Toshio Maeda, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.