A. Chou

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

D. Daley, L. Wagner, S. Narasimha, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Synthesis and control of ultra thin gate oxides for the 90 and 65 nm nodes

Wei He, Wenjuan Zhu, E. Rottenkolber, 2005, 2005 13th International Conference on Advanced Thermal Processing of Semiconductors.

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

V. Narayanan, R. Jammy, B.H. Lee, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Plasma damage and photo-annealing effects of thin gate oxides and oxynitrides during O2 plasma exposure

J.C. Lee, A. Chou, A. Chou, 1996, IEEE Electron Device Letters.

Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

Terence B. Hook, James H. Stathis, Ronald J. Bolam, 2005 .

Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide

A. Chou, A. Chou, G. Larosa, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices

S. Narasimha, T. Yamashita, H. Bu, 2013, 2013 Symposium on VLSI Technology.