David Lattimore

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

Andrew Morgan, Greg Patterson, Jeff Bray, 2010, IEEE Journal of Solid-State Circuits.

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration

Greg Patterson, Jeff Bray, Carroll Speir, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).