Yukio Mitsuyama

发表

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Shusuke Yoshimoto, Hiroshi Kawaguchi, Yukio Mitsuyama, 2018, VLSI Design and Test for Systems Dependability.

Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2009, 2009 Asia and South Pacific Design Automation Conference.

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Measurement of Variations in FPGAs under Various Load Conditions

Yukio Mitsuyama, Takashi Asada, Makio Eguchi, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Coarse-grained dynamically reconfigurable architecture with flexible reliability

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2009, 2009 International Conference on Field Programmable Logic and Applications.

VLSI architecture of burst mode acceleration for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2005 .

Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs

Yukio Mitsuyama, Kojiro Ito, Masanori Hashimoto, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

Masanori Hashimoto, Dawood Alnajiar, Yukio Mitsuyama, 2013, IEICE Electron. Express.

Variability and Soft-Error Resilience in Dependable VLSI Platform

Yukio Mitsuyama, Hidetoshi Onodera, H. Onodera, 2014, 2014 IEEE 23rd Asian Test Symposium.

A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, WISA.

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

Masanori Hashimoto, Dawood Alnajiar, Yukio Mitsuyama, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2009, IEICE Trans. Electron..

A dynamically reconfigurable hardware-based cipher chip

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2001, ASP-DAC '01.

A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2013, IEEE Transactions on Information Forensics and Security.

Development of Autonomous Driving System Using Programmable SoCs

Yukio Mitsuyama, Wang Liao, Tomonari Tanaka, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

Burst mode: a new acceleration mode for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Placement and routing for enhancing fault avoidance by dynamically partial reconfiguration

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2014 .

NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2011, PATMOS.

Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Area-Efficient Reconfigurable Architecture for Media Processing

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2015, The 20th Asia and South Pacific Design Automation Conference.

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VLSI implementation of high performance burst mode for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

FeRAM circuit technology for system on a chip

Teresa H. Y. Meng, Yukio Mitsuyama, Takao Onoye, 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Performance variation measurement on commercial FPGAs under various operating conditions

Yukio Mitsuyama, Takashi Asada, Makio Eguchi, 2016, 2016 IEEE Region 10 Conference (TENCON).

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2013, IEICE Trans. Inf. Syst..

Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture

Masanori Hashimoto, Hiroaki Konoura, Dawood Alnajiar, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2009 .

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Novel processor architecture for onboard infrared sensors

Yukio Mitsuyama, Hiroyuki Ochi, Kazutoshi Wakabayashi, 2016, Optical Engineering + Applications.

Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2008, GLSVLSI '08.

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars

Masanori Hashimoto, Yukio Mitsuyama, Kazutoshi Wakabayashi, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Kanbara, 2018, IEEE Embedded Systems Letters.

Atomic Switch FPGA: Application for IoT Sensing Systems in Space

Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, 2020 .

Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space

Yukio Mitsuyama, Hiroyuki Ochi, Kazutoshi Wakabayashi, 2019 .

Potential Energy-Based Center of Gravity Evaluation of Characters

Yukio Mitsuyama, Takao Onoye, Nakamura Yasuhisa, 2006 .

Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Stress Probability Computation for Estimating NBTI-Induced Delay Degradation

Masanori Hashimoto, Hiroaki Konoura, Yukio Mitsuyama, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2009, ISLPED.

Soft error resilient VLSI architecture for signal processing

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

VLSI architecture of dynamically reconfigurable hardware-based cipher

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Design Flow and Design Tools

Yukio Mitsuyama, Tomonori Izumi, T. Izumi, 2018, Principles and Structures of FPGAs.

Development of Autonomous Driving System based on Image Recognition using Programmable SoCs

Yukio Mitsuyama, Ryohei Yamamoto, Yuki Izumi, 2021, 2021 International Conference on Field-Programmable Technology (ICFPT).

Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2010, 2010 IEEE International Reliability Physics Symposium.

Neutron induced single event multiple transients with voltage scaling and body biasing

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2011, 2011 International Reliability Physics Symposium.

Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement

Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye, 2013, IEEE Transactions on Nuclear Science.