Tokuo Kure

发表

A charge recycle refresh for Gb-scale DRAM's in file applications

Masashi Horiguchi, Takayuki Kawahara, Takesada Akiba, 1994 .

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

Koichiro Ishibashi, Hiroyuki Mizuno, Tokuo Kure, 1996 .

256 Mb DRAM technologies for file applications

Masashi Horiguchi, Takashi Nishida, Norio Hasegawa, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

29 ps ECL circuits using U-groove isolated SICOS technology

Yoichi Tamaki, Tokuo Kure, Takashi Kobayashi, 1989, International Technical Digest on Electron Devices Meeting.

Semiconductor memory and its manufacturing processes.

Tokuo Kure, Hideo Sunami, Yoshifumi Kawamoto, 1983 .

Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring

Kiyoo Itoh, Yoshinobu Nakagome, Tokuo Kure, 1988 .

4829361 Semiconductor device

Kazuo Nakazato, Noriyuki Homma, Kazuhiko Sagara, 1990 .

Effects of Floating Gate Structure on Reliability in Flash Memories

Tokuo Kure, Toshihiro Tanaka, Tetsuo Adachi, 1994 .

A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory

Takashi Nishida, Tokuo Kure, Hiroshi Ishida, 1997 .

Scaling considerations and dielectric breakdown improvement of a corrugated capacitor cell for a future dRAM

Tokuo Kure, Hideo Sunami, H. Miyazawa, 1985 .

Single-electron memory for giga-to-tera bit storage

Kazuo Yano, Fumio Murai, Tokuo Kure, 1999, Proc. IEEE.

A 2.3m2, Single-Bit-Line SRAM Cell with High Soft-Error-Immune Structure

Eiji Takeda, Tokuo Kure, Hiroshi Ishida, 1993 .

256-Mb DRAM circuit technologies for file applications

Masashi Horiguchi, Takashi Nishida, Norio Hasegawa, 1993 .

Study of Si-coupled superconducting FETs using microfabrication technologies

Fumio Murai, Tokuo Kure, Toshikazu Nishino, 1990, Other Conferences.

A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

Eiji Takeda, Norio Hasegawa, J. Yugami, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology

Fumio Murai, Tokuo Kure, Takahiro Onai, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Low‐temperature dry etching

Tokuo Kure, Kazunori Tsujimoto, T. Kure, 1991 .

Analysis of Polymer Formation during SiO2 Microwave Plasma Etching

Tokuo Kure, Yasushi Gotoh, 1995 .

A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line

Kiyoo Itoh, Eiji Takeda, Norio Hasegawa, 1990 .

Multilevel interconnection for half-micron ULSI's

Tokuo Kure, Takashi Nishida, K. Yagi, 1989, Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.

Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI

Eiji Takeda, R. Izawa, Tokuo Kure, 1988 .

Observation of deep contact holes and conductive components underlying insulator in a memory cell by tunneling acoustic microscopy

Tokuo Kure, Keiji Takata, T. Kure, 1992 .

A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell

Atsushi Hiraiwa, Tokuo Kure, Hideo Sunami, 1988 .

A 0.5- mu m very-high-speed silicon bipolar devices technology U-groove-isolated SICOS

Yoichi Tamaki, Tokuo Kure, Takeo Shiba, 1991 .

0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)

Shinji Okazaki, Tokuo Kure, Katsuhiro Shimohigashi, 1990, International Technical Digest on Electron Devices.

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

Kiyoo Itoh, Fumio Murai, Tokuo Kure, 1991 .

Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.

Kiyoo Itoh, Norio Hasegawa, Atsushi Hiraiwa, 1988 .

Evaluation of Dislocation Generation in U‐Groove Isolation

Yoichi Tamaki, Tokuo Kure, Masao Kawamura, 1988 .

A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits

Koichiro Ishibashi, Tokuo Kure, Takashi Nishida, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

A 64 GHz Si bipolar transistor using in-situ phosphorus doped polysilicon emitter technology

Tokuo Kure, M. Tanabe, S. Iijima, 1991, International Electron Devices Meeting 1991 [Technical Digest].

U-Groove Isolation Technology for High Density Bipolar LSI's

Yoichi Tamaki, Tokuo Kure, Hisayuki Higuchi, 1982 .

A Buried Giga-Ohm Resistor(BGR) Load Static RAM Cell

Tokuo Kure, Toshiaki Yamanaka, Osamu Minato, 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

A corrugated capacitor cell (CCC) for megabit dynamic MOS memories

Kiyoo Itoh, Toru Toyabe, Tokuo Kure, 1982 .