Martin Margala

发表

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform

Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

Martin Margala, Marco Lanuzza, Stefania Perri, 2008, PATMOS.

Varicap threshold logic

Martin Margala, Samed Maltabas, Ugur Çilingiroglu, 2009, GLSVLSI '09.

Terahertz travelling wave amplifier design using Ballistic Deflection Transistor

Martin Margala, Huan Wang, Jean-François Millithaler, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders

Martin Margala, Michael Wieckowski, 2004, IEEE International SOC Conference, 2004. Proceedings..

Minimizing concurrent test time in SoC's by balancing resource usage

Martin Margala, Shambhu Upadhyaya, Dan Zhao, 2002, GLSVLSI '02.

Document classification systems in heterogeneous computing environments

Martin Margala, Wim Vanderbauwhede, Nasibeh Nasiri, 2016, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Power supply current test approach for resistive fault screening in embedded analog circuits

Martin Margala, Marco S. Dragic, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits

Fabrizio Lombardi, Martin Margala, Pilin Junsangsri, 2017, ACM Great Lakes Symposium on VLSI.

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications

Martin Margala, Marco Lanuzza, Stefania Perri, 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits

Martin Margala, John Liobe, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

Martin Margala, Pasquale Corsonello, Sai Rahul Chalamalasetti, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

High level programming framework for FPGAs in the data center

Martin Margala, Oren Segal, Sai Rahul Chalamalasetti, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A portless SRAM Cell using stunted wordline drivers

Martin Margala, Michael Wieckowski, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A Processor-In-Memory Architecture for Multimedia Compression

Martin Margala, Brandon J. Jasionowski, Michelle K. Lay, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2009, 2009 International Conference on Field Programmable Logic and Applications.

AutoML for Multilayer Perceptron and FPGA Co-design pdf

Martin Margala, Oren Segal, Philip Colangelo, 2020, ArXiv.

Neural networks-based parametric testing of analog IC

Martin Margala, Viera Stopjaková, Lubica Benusková, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Cost model analysis of DFT based fault tolerant SOC designs

Martin Margala, Shambhu J. Upadhyaya, Karthik Sundararaman, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time

Martin Margala, Sadeka Ali, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A 1.2 V built-in architecture for high frequency on-line Iddq/delta Iddq test

Martin Margala, Srdjan Dragic, 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

Design verification and DFT for an embedded reconfigurable low-power multiplier in system-on-chip applications

Jian Xu, Martin Margala, Xianling Chen, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

A CMOS Ripple Detector for Voltage Regulator Testing

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2016, J. Electron. Test..

A new SoC test architecture with RF/wireless connectivity

Martin Margala, Shambhu J. Upadhyaya, Dan Zhao, 2005, European Test Symposium (ETS'05).

1.8V 0.18µm CMOS Novel Successive Approximation ADC

Martin Margala, Quentin Diduck, Eric Moule, 2003, VLSI-SOC.

Evolutionary Cell Aided Design for Neural Network Architectures pdf

Martin Margala, Philip Colangelo, Oren Segal, 2019, ArXiv.

Low Overhead Radiation Hardening Techniques for Embedded Architectures

Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, 2012 .

Topology impact on the room temperature performance of THz-range ballistic deflection transistors

Martin Margala, Vikas Kaushal, Ignacio Iñiguez-de-la-Torre, 2010, GLSVLSI '10.

VLSI-SoC: At the Crossroads of Emerging Trends

Martin Margala, Alex Orailoglu, Ricardo Reis, 2013, IFIP Advances in Information and Communication Technology.

An FPGA memcached appliance

Martin Margala, Kevin T. Lim, Parthasarathy Ranganathan, 2013, FPGA '13.

An IDDQ BIST approach to characterize phase-locked loop parameters

Martin Margala, Samed Maltabas, Kemal Kulovic, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2009, ERSA.

Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance

Martin Margala, Sohan Purohit, M. Margala, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits

Martin Margala, Samed Maltabas, Osman Kubilay Ekekon, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A Self-Biased Charge-Transfer Sense Amplifier

Martin Margala, Sandeep Patil, Michael Wieckowski, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Martin Margala, Zhuo Qian, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Using computational RAM for volume rendering

Martin Margala, Nelson G. Durdle, D. G. Elliott, 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

Evaluating FPGA-acceleration for Real-time

Martin Margala, Wim Vanderbauwhede, Parthasarathy Ranganathan, 2012 .

New Embedded Core Testing for System-on-Chips and System-in-Packages

Martin Margala, Yuxin Wang, 2006, 2006 Canadian Conference on Electrical and Computer Engineering.

An integrated countermeasure against differential power analysis for secure smart-cards

Martin Margala, Stefania Perri, Pasquale Corsonello, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test

Martin Margala, John Liobe, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor

Martin Margala, Rong Lin, 2002, GLSVLSI '02.

A current based self-test methodology for RF front-end circuits

Martin Margala, P. R. Mukund, Anand Gopalan, 2005, Microelectron. J..

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2018, J. Electron. Test..

A novel low-power and in-place split-radix FFT processor

Martin Margala, Zhuo Qian, 2014, GLSVLSI '14.

Column-wise ROIC design with on-chip calibration for photoresistive image sensor

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2017, 2017 European Conference on Circuit Theory and Design (ECCTD).

Tutorial: RAM-basedCircuits andArchitectures forMultimedia andSignal Processing SOCs

Martin Margala, 2006 .

Control constrained resource partitioning for complex SoCs [intra-chip wireless interconnects]

Martin Margala, Shambhu J. Upadhyaya, Dan Zhao, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Evaluating FPGA-acceleration for real-time unstructured search

Martin Margala, Wim Vanderbauwhede, Parthasarathy Ranganathan, 2012, 2012 IEEE International Symposium on Performance Analysis of Systems & Software.

Low-Power Memory Circuits

Martin Margala, 1999, The VLSI Handbook.

Study of leakage current mechanisms in ballistic deflection transistors

Martin Margala, Vikas Kaushal, Quentin Diduck, 2009, GLSVLSI '09.

On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects

Martin Margala, Yuxin Wang, D. Makadia, 2006, 2006 Canadian Conference on Electrical and Computer Engineering.

A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2011, 2011 International Conference on High Performance Computing & Simulation.

Session details: Keynote IV

Martin Margala, 2015, GLSVLSI 2015.

Sobel edge detection processor for a real-time volume rendering system

Martin Margala, Nelson G. Durdle, Natalia Kazakova, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform

Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, 2010, 2010 Sixth International Conference on Information Assurance and Security.

Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs

Martin Margala, Philip Colangelo, Shayan Sengupta, 2020, ISCAS.

Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability

Martin Margala, Kemal Kulovic, 2012, J. Electron. Test..

Process tolerant calibration circuit for PLL applications with BIST

Martin Margala, Sadeka Ali, John Liobe, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Low-voltage power-efficient BiDPL logic design and applications

Martin Margala, Nelson G. Durdle, N. L. Rodnunsky, 1998, Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341).

Testing of deep-submicron battery-operated circuits using new fast current monitoring scheme

Martin Margala, I. Pecuh, 2000, Proceedings 2000 IEEE International Workshop on Defect Based Testing (Cat. No.PR00637).

Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip

Martin Margala, Shambhu J. Upadhyaya, Dan Zhao, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low Power SRAMs for Battery Operation

Martin Margala, 1999, MTDT.

A 33MHz 16. Bit Gradient Calculator for Real-Time Volume Imaging

Martin Margala, Nelson G. Durdle, Doug L. Hill, 1994, Workshop on Graphics Hardware.

Power minimization methodology for VCTL topologies

Martin Margala, Samed Maltabas, Ugur Çilingiroglu, 2010, 23rd IEEE International SOC Conference.

A Versatile Computation ModuleforAdaptable Multimedia Processors

Martin Margala, 2006 .

A versatile computation module for adaptable multimedia processors

Martin Margala, Yunan Xiang, R. Pettibon, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs

Martin Margala, Eriko Nurvitadhi, Asit K. Mishra, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems pdf

Martin Margala, Nasibeh Nasiri, Oren Segal, 2016, ArXiv.

FPGA implementation of low-power split-radix FFT processors

Martin Margala, Nasibeh Nasiri, Oren Segal, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Efficient addition circuits for Modular design of processors-in-memory

Martin Margala, Stefania Perri, Pasquale Corsonello, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low power RAM-based hierarchical CAM on FPGA

Martin Margala, Zhuo Qian, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

A novel self-repairable parallel multiplier architecture, design and test

Martin Margala, Rong Lin, N. Kazakova, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

A Digital BIST for Phase-Locked Loops

Martin Margala, Kevin Sliech, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs

Martin Margala, Eriko Nurvitadhi, Asit K. Mishra, 2018, FCCM.

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

Martin Margala, John Liobe, Richard Geisler, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA

Martin Margala, Enno Lübbers, Randy Huang, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, J. Low Power Electron..

Compact Implementation of BLUE MIDNIGHT WISH-256 Hash Function on Xilinx FPGA Platform

Martin Margala, Danilo Gligoroski, Svein J. Knapskog, 2010, IAS 2010.

Process and Temperature Calibration of PLLs with BiST Capabilities

Martin Margala, John Liobe, Richard Geisler, 2007, 2007 IEEE International Symposium on Circuits and Systems.

New performance/power/area efficient, reliable full adder design

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2009, GLSVLSI '09.

Modeling and study of two-BDT-nanostructure based sequential logic circuits

Martin Margala, Jean-François Millithaler, Ignacio Iñiguez-de-la-Torre, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

FPGAs for Domain Experts

Martin Margala, Wim Vanderbauwhede, Sven-Bodo Scholz, 2020, Int. J. Reconfigurable Comput..

Functional Safety of a Lidar Sensor System

Martin Margala, Bhanu Singh, Sharath Patil, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder

Martin Margala, Marco Lanuzza, Sohan Purohit, 2010, J. Low Power Electron..

A high performance Full Adder based on Ballistic Deflection Transistor technology

Martin Margala, Jean-François Millithaler, Ignacio Iñiguez-de-la-Torre, 2017, International Symposium on Circuits and Systems.

High-Performance FPGA-Accelerated Real-Time Search

Martin Margala, Wim Vanderbauwhede, Sai. R. Chalamalasetti, 2013 .

High level programming of FPGAs for HPC and data centric applications

Martin Margala, Wim Vanderbauwhede, Nasibeh Nasiri, 2014, 2014 IEEE High Performance Extreme Computing Conference (HPEC).

A new test methodology for DNL error in flash ADCs

Martin Margala, Michael Wieckowski, John Liobe, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only)

Martin Margala, Wim Vanderbauwhede, Nasibeh Nasiri, 2015, FPGA.

Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms

Martin Margala, Oren Segal, Philip Colangelo, 2019, 2019 IEEE High Performance Extreme Computing Conference (HPEC).

Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters

Martin Margala, John Liobe, Quentin Diduck, 2003, VLSI-SOC.

Adaptable Architectures for Signal Processing Applications

Martin Margala, 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

Ballistic deflection transistors and the emerging nanoscale era

Paul Ampadu, Martin Margala, Roman Sobolewski, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

Martin Margala, Marco Lanuzza, Stefania Perri, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Design of wireless sub-micron characterization system

Martin Margala, Christopher J. Backhouse, Brian Moore, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

5-Gb/s linear re-driver in 180 nm CMOS technology

Martin Margala, Phuc Pham, Hieu Nguyen, 2018, Microelectron. J..

Design of self correcting radiation hardened digital circuits using decoupled ground bus

Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, 2010, GLSVLSI '10.

A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic

Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, 2009, GLSVLSI '09.

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters pdf

Martin Margala, Nasibeh Nasiri, Philip Colangelo, 2015, ArXiv.

A novel five-transistor (5T) sram cell for high performance cache

Martin Margala, Michael Wieckowski, 2005, Proceedings 2005 IEEE International SOC Conference.

A versatile built-in CMOS sensing device for digital circuit parametric test

Martin Margala, Marco S. Dragic, 2003, IEEE Trans. Instrum. Meas..

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing

Martin Margala, Pasquale Corsonello, Sai Rahul Chalamalasetti, 2008, 2008 IEEE International SOC Conference.

A new level sensitive D Latch using Ballistic nanodevices

Martin Margala, Jean-François Millithaler, Poorna Marthi, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

MORA: High-Level FPGA Programming Using a Many-Core Framework

Martin Margala, Wim Vanderbauwhede, Sai. R. Chalamalasetti, 2013, Multicore Technology.

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

Martin Margala, Viera Stopjaková, Marek Matej, 2004, J. Electron. Test..

ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2017, 2017 New Generation of CAS (NGCAS).

Proceedings of the 26th edition on Great Lakes Symposium on VLSI

Martin Margala, Jie Han, Laleh Behjat, 2016, ACM Great Lakes Symposium on VLSI.

Highly efficient digital CMOS accelerator for image and graphics processing

Martin Margala, Rong Lin, 2002, 15th Annual IEEE International ASIC/SOC Conference.

A C++-embedded Domain-Specific Language for programming the MORA soft processor array

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Fast and low-power inner product processor

Martin Margala, Nelson G. Durdle, Julien Lamoureux, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Control Constrained Resource Partitioning for Complex SoCs

Martin Margala, Shambhu Upadhyaya, Dan Zhao, 2003 .

A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)

Martin Margala, Zhuo Qian, 2015, FPGA.

A high frequency, low jitter auto-calibration phase-locked loop with built-in-self-test

Martin Margala, Sadeka Ali, Gregory Briggs, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler

Martin Margala, Huan Wang, Jean-François Millithaler, 2018, 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS).

High Level Programming for Heterogeneous Architectures pdf

Martin Margala, Oren Segal, Sai Rahul Chalamalasetti, 2014, ArXiv.

A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies

Martin Margala, Samed Maltabas, Osman Kubilay Ekekon, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud

Martin Margala, Oren Segal, 2016, 2016 International Conference on High Performance Computing & Simulation (HPCS).

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems

Mohamed El-Hadedy, Martin Margala, Sohan Purohit, 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

A new built-in IDDQ testing method using programmable BICS

Martin Margala, Samed Maltabas, Osman Kubilay Ekekon, 2010, 2010 15th IEEE European Test Symposium.

Novel Practical Built-in Current Sensors

Martin Margala, Samed Maltabas, Kemal Kulovic, 2012, J. Electron. Test..

Low-power SRAM circuit design

Martin Margala, 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs

Martin Margala, 2006, 2006 IEEE International SOC Conference.

Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems

Kevin Skadron, Martin Margala, Mircea R. Stan, 2016, Journal of Signal Processing Systems.

A droop measurement built-in self-test circuit for digital low-dropout regulators

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Alex K. Jones, Martin Margala, Hai Li, 2015, ACM Great Lakes Symposium on VLSI.

Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications

Jinjun Xiong, Martin Margala, Wen-Mei Hwu, 2020, 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A CMOS ripple detector for integrated voltage regulator testing

Martin Margala, Cagatay Ozmen, Aydin Dirican, 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

Defect detection in analog and mixed circuits by neural networks using wavelet analysis

Martin Margala, Viera Stopjaková, Vladislav Nagy, 2005, IEEE Transactions on Reliability.

Radiation-Hardened Reconfigurable Array With Instruction Roll-Back

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2010, IEEE Embedded Systems Letters.

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, 2009 22nd International Conference on VLSI Design.

Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations

Martin Margala, Jean-François Millithaler, Ignacio Iñiguez-de-la-Torre, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

High throughput filtering using FPGA-acceleration

Martin Margala, Wim Vanderbauwhede, Leif Azzopardi, 2013, CIKM.

Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2012, Int. J. Reconfigurable Comput..

Aparapi-UCores: A high level programming framework for unconventional cores

Martin Margala, Nasibeh Nasiri, Philip Colangelo, 2015, 2015 IEEE High Performance Extreme Computing Conference (HPEC).

6-bit low power low area frequency modulation based flash ADC

Martin Margala, Quentin Diduck, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

An area efficient design methodology for SEU tolerant digital circuits

Martin Margala, David Harrington, Sohan Purohit, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Design of wireless on-wafer submicron characterization system

Martin Margala, Christopher J. Backhouse, Brian Moore, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low latency transpose memory for high throughput signal processing

Mohamed El-Hadedy, Martin Margala, Sohan Purohit, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths

Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

A current sensor for on-chip, non-intrusive testing of RF systems

Martin Margala, P. R. Mukund, Anand Gopalan, 2004, 17th International Conference on VLSI Design. Proceedings..

1-V ADPCM Processor for Low-Power Wireless Applications

Martin Margala, Wendi B. Heinzelman, Junmou Zhang, 2003, VLSI-SOC.

Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA

Martin Margala, Enno Lübbers, Randy Huang, 2017, 2017 IEEE High Performance Extreme Computing Conference (HPEC).

New approach to design for reusability of arithmetic cores in systems-on-chip

Martin Margala, Hongfan Wang, M. Margala, 2004, Integr..

A VHDL implementation of a shearing unit for shear-warp factorization volume rendering

Martin Margala, N. Kazakova, M. Margala, 2000, 2000 Canadian Conference on Electrical and Computer Engineering. Conference Proceedings. Navigating to a New Era (Cat. No.00TH8492).

A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2014, CARN.

Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors

Martin Margala, David H. Albonesi, Jason Martin, 2001, VLSI-SOC.

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ballistic deflection transistors and their application to THz amplification

Martin Margala, Roman Sobolewski, Hui Wu, 2015 .

Nonlinear characteristics of T-branch junctions: Transition from ballistic to diffusive regime

Martin Margala, Roman Sobolewski, Marc J. Feldman, 2008 .

A Design of Terahertz Parallel Plate Dielectric Waveguide with Signal Line inserted for Ballistic Deflection Transistor Travelling Wave Amplifier

Martin Margala, Ronald W. Knepper, P. Marthi, 2017 .