Tanaka Haruhiko

An experimental 1.5-V 64-Mb DRAM

Eiji Takeda, Kiyoo Itoh, R. Izawa, 1991 .

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Takeshi Sakata, Eiji Takeda, Mayu Aoki, 1995, IEEE J. Solid State Circuits.

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Kiyoo Itoh, Mayu Aoki, Y. Nakagome, 1988 .

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Mayu Aoki, T. Sakata, S. Kimura, 1999 .