Tadashi Ozawa

A 6ns 1Mb CMOS SRAM with Latched Sense Amplifier (Special Section on the 1992 VLSI Circuits Symposium)

Noriyuki Suzuki, Hiroyuki Sano, Teruo Seki, 1993 .

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

Noriyuki Suzuki, Teruo Seki, Eisaku Itoh, 1993 .

A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier

Teruo Seki, N. Suzuki, Eisaku Itoh, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

Comparison for Initialization by Various Balance Models and Mesh Sizes

Tadashi Ozawa, T. Ozawa, 1971 .