Peter Gregorius

发表

Forward equalizer and method for equalizing a data signal analog

Peter Gregorius, 2004 .

Semiconductor memory interface

Peter Gregorius, Paul Wallner, 2006 .

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Peter Gregorius, Michael Richter, Rex Kho, 2010, IEEE Journal of Solid-State Circuits.

Integrated memory device and method for operating an integrated memory chip

Peter Gregorius, Paul Wallner, Stefan Dietrich, 2006 .

Memory system with integrated memory devices and methods of operating a memory system

Peter Gregorius, Paul Wallner, 2006 .

An apparatus for reconstruction of data from a received data signal and corresponding transmitting and receiving device

Peter Gregorius, Torsten Hinz, 2001 .

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques

Peter Gregorius, Michael Richter, Rex Kho, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Apparatus for generating standard-compliant signals

Peter Gregorius, Thomas Duda, Jörg Dr.-Ing. Bonhaus, 2003 .

Storage system with enhanced storage density capability

Peter Gregorius, Hermann Ruckerbauer, Christoph Bilger, 2008 .

Adaptive Equalizer Training for High-Speed Low-Power Communication Systems

Ling Chen, Klaus Hofmann, Peter Gregorius, 2013, 2013 Euromicro Conference on Digital System Design.

A semiconductor memory system and method for transferring read and write data signals in a semiconductor memory system

Peter Gregorius, Hermann Ruckerbauer, Dominique Savignac, 2004 .

A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform

Klaus Hofmann, Peter Gregorius, Boris Traskov, 2013, 2013 IEEE Third International Conference on Consumer Electronics ¿ Berlin (ICCE-Berlin).

Memory device and method for generating a sample clock signal in a communications block of a memory device

Peter Gregorius, Martin Streibl, 2006 .

A method for reconstructing transmitted via a transmission path of data in a receiver and corresponding device

Peter Gregorius, Lajos Gazsi, 2001 .

Apparatus for data recovery from a received data signal

Peter Gregorius, Bernhard Engl, 2002 .

Hardware architecture of an Internet Protocol Version 6 processor

Klaus Hofmann, Peter Gregorius, Boris Traskov, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Circuit arrangement for clock and data recovery from a received signal

Peter Gregorius, Bernhard Engl, 2001 .

Integrated storage device and memory module

Peter Gregorius, Hermann Ruckerbauer, Dominique Savignac, 2005 .

Cascading Techniques for a High-Speed Memory Interface

Peter Gregorius, Hermann Ruckerbauer, Zheng Gu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

High-speed interface circuit for semiconductor memory chips and a memory system containing this

Peter Gregorius, Hermann Ruckerbauer, Paul Wallner, 2006 .

The semiconductor memory chip with routing means for electrical signals

Peter Gregorius, Hermann Ruckerbauer, 2006 .

Method for data transmission between different clock domains, corresponding apparatus and corresponding memory module

Peter Gregorius, Martin Streibl, Thomas Rickes, 2007 .

Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems

Klaus Hofmann, Peter Gregorius, Yuan Fang, 2013, 2013 Euromicro Conference on Digital System Design.

A device for controlled delay of a clock signal

Peter Gregorius, Andreas Jakobs, 2004 .