J. G. Nash

Hardware efficient base-4 systolic architecture for computing the discrete Fourier transform

J. G. Nash, J. Nash, 2002, IEEE Workshop on Signal Processing Systems.

Combinatorial digital logic using charge-coupled devices

J. G. Nash, 1982 .

Concurrent VLSI (Very Large Scale Integration) Architectures for Two Dimensional Signal Processing Systems

J. G. Nash, G. R. Nudd, 1983 .

Heterogeneous algorithms for image understanding architecture

J. G. Nash, David B. Shu, M. M. Eshaghian, 1993, 1993 Computer Architectures for Machine Perception.

VLSI Processor Arrays for Matrix Manipulation

J. G. Nash, G. R. Nudd, S. Hansen, 1981 .

PARALLEL PROCESSING OF ICONIC TO SYMBOLIC TRANSFORMATION OF IMAGES.

J. G. Nash, D. I. Moldovan, Charles C. Weems, 1985 .

A multiple-level heterogeneous architecture for image understanding

Charles C. Weems, J. G. Nash, D. B. Shu, 1990, [1990] Proceedings. 10th International Conference on Pattern Recognition.

High-density electron-beam-fabricated CCD memory components

J. G. Nash, R. C. Henderson, J. Y. Chen, 1980 .