Matthew Horsnell

Scalable Object-Aware Hardware Transactional Memory

Mikel Luján, Ian Watson, Behram Khan, 2010, Euro-Par.

Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation

Andrew Dinn, Ian Watson, Ian Rogers, 2007, Euro-Par.

An adaptive bloom filter cache partitioning scheme for multicore architectures

Jim D. Garside, Matthew Horsnell, Konstantinos Nikas, 2008, 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation.

Flexible and High-Speed System-Level Performance Analysis using Hardware-Accelerated Simulation

Andreas Hansson, Bashir M. Al-Hashimi, Matthew Horsnell, 2013, DATE 2013.

Adaptive Loop Tiling for a Multi-cluster CMP

Mikel Luján, Ian Watson, Ian Rogers, 2008, ICA3PP.

An Object-Aware Hardware Transactional Memory System

Andrew Dinn, Mikel Luján, Ian Watson, 2008, 2008 10th IEEE International Conference on High Performance Computing and Communications.

The gem5 Simulator: Version 20.0+ pdf

Nikos Nikoleris, Yuetsu Kodama, Alec Roelke, 2020, ArXiv.

A first insight into object-aware hardware transactional memory

Andrew Dinn, Mikel Luján, Ian Watson, 2008, SPAA '08.

Exploiting object structure in hardware transactional memory

Andrew Dinn, Mikel Luján, Ian Rogers, 2009, Comput. Syst. Sci. Eng..

Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture

José L. Núñez-Yáñez, Matthew Horsnell, Krastin Nikov, 2015, 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing.