Jianghao Guo

Cross-Layer Fault-Tolerant Design and Analysis for High Manufacturing Yield and System Reliability

Jianghao Guo, 2016 .

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wen-Ben Jone, Shianling Wu, Xiaoqing Wen, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A cross-layer fault-tolerant design method for high manufacturing yield and system reliability

Wen-Ben Jone, Yu-Liang Wu, Jianghao Guo, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Turbo1500: Core-Based Design for Test and Diagnosis

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2009, IEEE Design & Test of Computers.

Path delay testing in resilient system

Wen-Ben Jone, Qiang Xu, Jianghao Guo, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

On Resilient System Performance Binning

Qiang Xu, Wen-Ben Jone, Jianghao Guo, 2015, ISPD.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2008, 2008 IEEE International Test Conference.