Cezar Reinbrecht

发表

Floorplan-aware hierarchical NoC topology with GALS interfaces

Luigi Carro, Debora Matos, Cezar Reinbrecht, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable

Cezar Reinbrecht, Bruno Forlin, Martha Johanna Sepúlveda, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

NoC Power Estimation at the RTL Abstraction Level

Fernando Gehm Moraes, Cezar Reinbrecht, Ney Laert Vilar Calazans, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

A Security Verification Template to Assess Cache Architecture Vulnerabilities

Cezar Reinbrecht, Jaan Raik, Said Hamdioui, 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip

Luigi Carro, Vittorio Zaccaria, Debora Matos, 2011, NoCArc '11.

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V

Cezar Reinbrecht, Ulf Schlichtmann, Martha Johanna Sepúlveda, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Increasing NoC power estimation accuracy through a rate-based model

Fernando Gehm Moraes, Cezar Reinbrecht, Guilherme Montez Guindani, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management

Cezar Reinbrecht, Altamiro Amadeu Susin, Martha Johanna Sepúlveda, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Cache timing attacks on NoC-based MPSoCs

Cezar Reinbrecht, Bruno Forlin, Martha Johanna Sepúlveda, 2019, Microprocess. Microsystems.

Towards Formal Verification of Cache Access-based Side-Channel Attacks

Cezar Reinbrecht, Jaan Raik, Johanna Sepulveda, 2019 .

Earthquake - A NoC-based optimized differential collision cache attack for MPSoCs

Cezar Reinbrecht, Bruno Forlin, Johanna Sepulveda, 2018 .

Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack

Cezar Reinbrecht, Altamiro Amadeu Susin, Martha Johanna Sepúlveda, 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

Adaptive multiple switching strategy toward an ideal NoC

Luigi Carro, Debora Matos, Cezar Reinbrecht, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

On the Aspects of MPSoCs Security: Avoiding Logical Attacks with Network-on-Chip

Cezar Reinbrecht, Bruno Forlin, Johanna Sepulveda, 2019, ISCAS 2019.

Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

Cezar Reinbrecht, Martha Johanna Sepúlveda, Siavoosh Payandeh Azad, 2018, SAMOS.

Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection

Cezar Reinbrecht, Altamiro Amadeu Susin, Martha Johanna Sepúlveda, 2017, Microprocess. Microsystems.

Side-channel protected MPSoC through secure real-time networks-on-chip

Leandro Soares Indrusiak, Cezar Reinbrecht, Martha Johanna Sepúlveda, 2019, Microprocess. Microsystems.

PHiCIT — Improving hierarchical Networks-on-Chip through 3D silicon photonics integration

Cezar Reinbrecht, Altamiro Amadeu Susin, Martha Johanna Sepúlveda, 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs

Cezar Reinbrecht, Bruno Forlin, Martha Johanna Sepúlveda, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

Debora Matos, Cezar Reinbrecht, Altamiro Amadeu Susin, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability

Luigi Carro, Debora Matos, Cezar Reinbrecht, 2013, ARC.

DHyANA: A NoC-based neural network hardware architecture

Cezar Reinbrecht, Ricardo Augusto da Luz Reis, Vitor V. Bandeira, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Security Aspects of Neuromorphic MPSoCs

Cezar Reinbrecht, Martha Johanna Sepúlveda, Jean-Philippe Diguet, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A high abstraction, high accuracy power estimation model for networks-on-chip

Leandro Soares Indrusiak, Fernando Gehm Moraes, Cezar Reinbrecht, 2009, SBCCI.

EGIS NoC: A secure-enhanced interconnection to prevent Architectural Channel Attacks

Cezar Reinbrecht, Bruno Forlin, Johanna Sepulveda, 2018 .

Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks

Cezar Reinbrecht, Abdullah Aljuffri, Said Hamdioui, 2021, 2021 IEEE 39th VLSI Test Symposium (VTS).

Verifying cache architecture vulnerabilities using a formal security verification flow

Cezar Reinbrecht, Jaan Raik, Said Hamdioui, 2021 .

Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron

Cezar Reinbrecht, Martha Johanna Sepúlveda, Abdullah Aljuffri, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

GRINCH: A Cache Attack against GIFT Lightweight Cipher

Cezar Reinbrecht, Martha Johanna Sepúlveda, Abdullah Aljuffri, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks

Cezar Reinbrecht, Abdullah Aljuffri, Said Hamdioui, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

LightRoAD: Lightweight Rowhammer Attack Detector

Cezar Reinbrecht, Martha Johanna Sepúlveda, Said Hamdioui, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).