Yun Qu

发表

High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA

Viktor K. Prasanna, Yun Qu, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2014, 2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR).

Scalable and dynamically updatable lookup engine for decision-trees on FPGA

Viktor K. Prasanna, Yun Qu, V. Prasanna, 2014, 2014 IEEE High Performance Extreme Computing Conference (HPEC).

Multi-AUV SOM task allocation algorithm considering initial orientation and ocean current environment

Simon X. Yang, Daqi Zhu, Yun Qu, 2019, Frontiers of Information Technology & Electronic Engineering.

Multi-stream Regular Expression Matching on FPGA

Viktor K. Prasanna, Yun Qu, Yi-Hua Edward Yang, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Power-efficient range-match-based packet classification on FPGA

Viktor K. Prasanna, Yun Qu, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

High-throughput hash-based online traffic classification engines on FPGA

Viktor K. Prasanna, Yun Qu, Vaibhav R. Gandhi, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Large-scale multi-flow regular expression matching on FPGA

Viktor K. Prasanna, Yun Qu, Yi-Hua Edward Yang, 2012, 2012 IEEE 13th International Conference on High Performance Switching and Routing.

Multi-core Implementation of Decomposition-Based Packet Classification Algorithms

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2013, PaCT.

Fast Online Set Intersection for Network Processing on FPGA

Viktor K. Prasanna, Yun Qu, 2016, IEEE Transactions on Parallel and Distributed Systems.

Architecture and performance models for scalable IP lookup engines on FPGA

Viktor K. Prasanna, Yun Qu, Yi-Hua Edward Yang, 2013, 2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR).

Packet Classification on Multi-core Platforms

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2015, Handbook on Data Centers.

Multi-core implementation of decomposition-based packet classification algorithms

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2013, The Journal of Supercomputing.

Prediction and verification of microRNAs related to proline accumulation under drought stress in potato

Ning Zhang, Di Wang, Yun Qu, 2013, Comput. Biol. Chem..

Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)

Viktor K. Prasanna, Yun Qu, 2013, FPGA '13.

Large-scale packet classification on FPGA

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2015, 2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

High-throughput traffic classification on multi-core processors

Viktor K. Prasanna, Yun Qu, Da Tong, 2014, 2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR).

Compact hash tables for decision-trees

Viktor K. Prasanna, Yun Qu, V. Prasanna, 2016, Parallel Comput..

Compact Hash Tables for High-Performance Traffic Classification on Multi-core Processors

Viktor K. Prasanna, Yun Qu, V. Prasanna, 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.

A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2014, International Journal of Parallel Programming.

Enabling High Throughput and Virtualization for Traffic Classification on FPGA

Viktor K. Prasanna, Yun Qu, V. Prasanna, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Viktor K. Prasanna, Yun Qu, V. Prasanna, 2016, IEEE Transactions on Parallel and Distributed Systems.

High-performance architecture for dynamically updatable packet classification on FPGA

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2013, Architectures for Networking and Communications Systems.

Optimized SOM Algorithm to Solve Problem of Invalid Task Allocation

Daqi Zhu, Yun Qu, Mingzhi Chen, 2019, ICIRA.

Fast dynamically updatable packet classifier on FPGA

Viktor K. Prasanna, Yun Qu, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Scalable Many-Field Packet Classification on Multi-core Processors

Viktor K. Prasanna, Shijie Zhou, Yun Qu, 2013, 2013 25th International Symposium on Computer Architecture and High Performance Computing.