Ludovic Tambour

Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip

Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, 2000, DIPES.

An efficient methodology and semi-automated flow for design and validation of complex digital signal processing ASICS macro-cells

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Pascal Urard, 2003, 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings..

Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Henri Michel, 2005, Tech. Sci. Informatiques.

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Pascal Urard, 2006, EURASIP J. Adv. Signal Process..

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Ludovic Tambour, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.