Mizuno Hiroyuki

An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping

Yamada Kaito, Mase Masayoshi, Shirako Jun, 2008 .

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme

Namiki Mitaro, Sato Mikiko, Shirako Jun, 2010 .

Design Method of Lumped-Element Dual-Bnad Wilkinson Power Dividers

Mizuno Hiroyuki, Kawai Tadashi, Enokihara Akira, 2010 .

Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs

Hattori Toshihiro, Mizuno Hiroyuki, Irita Takahiro, 2006 .

Broadband Compact Rat-Race Circuits Using Composite Right-/Left-Handed Transmission Lines

Mizuno Hiroyuki, Kawai Tadashi, Enokihara Akira, 2009 .

CMOSアニーリングを用いた組合せ最適化問題を解くための20kスピンIsingチップ【Powered by NICT】

Aoki Hidetaka, Yamaoka Masanao, Mizuno Hiroyuki, 2016 .

Unequal Wilkinson Power Dividers with In-/Reverse-Phase Using Lumped-Element Circuits

Mizuno Hiroyuki, Kawai Tadashi, Ohta Isao, 2008 .