T. Sasaki

Electromagnetic Band Gap structure for cut off of low frequency noise in 3-D printed circuit board

T. Sasaki, H. Yamada, K. Itaya, 2012, 2012 2nd IEEE CPMT Symposium Japan.

A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

T. Sasaki, K. Kushida, A. Suzuki, 2008, 2008 IEEE Symposium on VLSI Circuits.

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

T. Sasaki, K. Kushida, A. Suzuki, 2009, IEEE Journal of Solid-State Circuits.

An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system

T. Sasaki, Y. Kitaura, T. Seshita, 1989, 11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium.

Analysis of PAE 50% highly linear characteristics of new structure transistor "self-aligned gate PHEMT" for W-CDMA application

T. Sasaki, T. Nitta, Y. Kitaura, 1999, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 21st Annual. Technical Digest 1999 (Cat. No.99CH36369).

Development of high sensitive water monitor protected with ice layer

T. Sasaki, Y. Yuasa, H. Nagao, 1980 .

Melt-segregate-quench programming of electrical fuse

T. Sasaki, S. Fujii, N. Otsuka, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

A 1.9 GHz SPDT switch implemented with GaN HFETs featuring two different depth-recesses in i-AlGaN

T. Sasaki, M. Hirose, K. Tsuda, 2004, IEEE Compound Semiconductor Integrated Circuit Symposium, 2004..