Chien-Hen Chen

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

Yi-Wei Lin, Hao-I Yang, Wei-Chiang Shih, 2012, 2012 IEEE International SOC Conference.

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Yi-Wei Lin, Hao-I Yang, Wei-Chiang Shih, 2011, 2011 IEEE International SOC Conference.