Yong-Jyun Hu

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

3-D Content Addressable Memory Architectures

Yu-Jen Huang, Jin-Fu Li, Yong-Jyun Hu, 2009, 2009 IEEE International Workshop on Memory Technology, Design, and Testing.

內容定址記憶體之三維架構探索與測試 ; Three-Dimensional Architecture Exploration and Testing of Content Addressable Memories

Yong-Jyun Hu, 胡詠鈞, 2010 .

Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells

Yu-Jen Huang, Jin-Fu Li, Yong-Jyun Hu, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2013, 2013 IEEE International SOC Conference.

Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells

Yu-Jen Huang, Jin-Fu Li, Yong-Jyun Hu, 2009, 2009 27th IEEE VLSI Test Symposium.