Viktor Pus

发表

Architecture of Effective High-Speed Network Stream Merger

Hana Kubatova, Pavel Benácek, Viktor Pus, 2014, 2014 17th Euromicro Conference on Digital System Design.

Viktor Pus, Petr Velan, V. Pus, 2015, 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM).

Low-latency modular packet header parser for FPGA

Jan Korenek, Viktor Pus, Lukas Kekely, 2012, 2012 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

Hardware accelerated flow measurement of 100 Gb ethernet

Jan Korenek, Viktor Pus, Petr Velan, 2015, 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM).

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput

Jan Korenek, Viktor Pus, Lukás Kekely, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Hardware Acceleration for Measurements in 100 Gb/s Networks

Viktor Pus, 2012, AIMS.

Building a feedback loop to capture evidence of network incidents

Viktor Pus, Tomás Cejka, Martin Zádník, 2016, 2016 12th International Conference on Network and Service Management (CNSM).

Memory optimizations for packet classification algorithms in FPGA

Jan Korenek, Viktor Pus, Juraj Blaho, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Reducing memory in high-speed packet classification

Jan Korenek, Viktor Pus, 2012, 2012 8th International Wireless Communications and Mobile Computing Conference (IWCMC).

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Hana Kubatova, Pavel Benácek, Viktor Pus, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Memory optimization for packet classification algorithms

Jan Korenek, Viktor Pus, Juraj Blaho, 2009, ANCS '09.

Design methodology of configurable high performance packet parser for FPGA

Jan Korenek, Viktor Pus, Lukas Kekely, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Netbench: Framework for Evaluation of Packet Processing Algorithms

Jan Korenek, Viktor Pus, Vlastimil Kosar, 2011, 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems.

Software Defined Monitoring of application protocols

Jan Korenek, Viktor Pus, Lukas Kekely, 2014, IEEE INFOCOM 2014 - IEEE Conference on Computer Communications.

CRC based hashing in FPGA using DSP blocks

Viktor Pus, Lukas Kekely, Tomás Závodník, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Fast and scalable packet classification using perfect hash functions

Jan Korenek, Viktor Pus, 2009, FPGA '09.

Application specific processor with high level synthesized instructions (abstract only)

Pavel Benácek, Viktor Pus, 2014, FPGA.

Algoritmy klasifikace paketů ; Packet Classification Algorithms

Viktor Pus, 2012 .

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring

Jan Korenek, Pavel Benácek, Viktor Pus, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Hardware architecture for packet classification with prefix coloring

Jan Korenek, Viktor Pus, Michal Kajan, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Line rate programmable packet processing in 100Gb networks

Jan Korenek, Pavel Benácek, Viktor Pus, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Software Defined Monitoring of Application Protocols

Athanasios V. Vasilakos, Jan Korenek, Viktor Pus, 2016, IEEE Transactions on Computers.

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Jan Korenek, Pavel Benácek, Viktor Pus, 2018, FPGA.

Monitoring, Detection and Reporting of Security Incidents inCESNET NREN

Pavel Čeleda, Viktor Pus, Petr Velan, 2013 .

Using DSP blocks to compute CRC hash in FPGA (abstract only)

Viktor Pus, Lukas Kekely, Tomás Závodník, 2014, FPGA.

P4-To-VHDL: Automatic generation of high-speed input and output network blocks

Hana Kubatova, Pavel Benácek, Viktor Pus, 2018, Microprocess. Microsystems.