Resve A. Saleh

发表

Design of a switch for network on chip applications

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An improved "soft" eFPGA design and implementation strategy

Guy Lemieux, Resve A. Saleh, Victor Aken Ova, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Compaction of ATPG-generated test sequences for sequential circuits

Janak H. Patel, Jacob A. Abraham, Resve A. Saleh, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT

Rabab Kreidieh Ward, Resve A. Saleh, Steven J. E. Wilton, 2009, 2009 IEEE International SOC Conference (SOCC).

Parallel waveform-Newton algorithms for circuit simulation

Resve A. Saleh, Eugene Z. Xia, R. Saleh, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-delay metrics revisited for 90 nm CMOS technology

Resve A. Saleh, Dipanjan Sengupta, 2005, Sixth international symposium on quality electronic design (isqed'05).

A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique

Shahriar Mirabbasi, Resve A. Saleh, Arash Zargaran-Yazd, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Incremental techniques for the identification of statically sensitizable critical paths

Resve A. Saleh, Yun-Cheng Ju, R. Saleh, 1991, 28th ACM/IEEE Design Automation Conference.

Timing analysis of network on chip architectures for MP-SoC platforms

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2005, Microelectron. J..

An Improved Active Decoupling Capacitor for “Hot-Spot” Supply Noise Reduction in ASIC Designs

Resve A. Saleh, Xiongfei Meng, 2009, IEEE Journal of Solid-State Circuits.

Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design

Resve A. Saleh, Dipanjan Sengupta, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance

Resve A. Saleh, Jeff Mueller, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Testing Network-on-Chip Communication Fabrics

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation

A. Richard Newton, Resve A. Saleh, R. Saleh, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

BIST for network-on-chip interconnect infrastructures

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2006, 24th IEEE VLSI Test Symposium.

Parallel circuit simulation using hierarchical relaxation

Resve A. Saleh, Kyle A. Gallivan, Yen-Cheng Wen, 1991, DAC '90.

An approach that will NoC your SoCs off!

Resve A. Saleh, 2005, IEEE Des. Test Comput..

Design, synthesis, and test of networks on chips

Giovanni De Micheli, Partha Pratim Pande, Cristian Grecu, 2005, IEEE Design & Test of Computers.

Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement

Resve A. Saleh, Jacob K. White, R. Saleh, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fast configuration of an energy-efficient branch predictor

Resve A. Saleh, Peter Hallschmid, R. Saleh, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Power Supply Noise in SoCs: Metrics, Management, and Measurement

Resve A. Saleh, Karim Arabi, Xiongfei Meng, 2007, IEEE Design & Test of Computers.

DFM--EDA's Salvation or its Excuse for Being out of Touch with Engineering?

Resve A. Saleh, Joseph Sawicki, Pallab K. Chatterjee, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Mixed-mode incremental simulation and concurrent fault simulation

Resve A. Saleh, Yun-Cheng Ju, Fred L. Yang, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Application-driven floorplan-aware voltage island design

Resve A. Saleh, Dipanjan Sengupta, 2008, 2008 45th ACM/IEEE Design Automation Conference.

The application of complex quantized feedback in integrated wireless receivers

Shahriar Mirabbasi, Resve A. Saleh, Zahra Sadat Ebadi, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Sequence pair based voltage island floorplanning

André Ivanov, Resve A. Saleh, Andreas G. Veneris, 2011, 2011 International Green Computing Conference and Workshops.

Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS

Resve A. Saleh, Karim Arabi, Xiongfei Meng, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Delay macromodeling and estimation for RTL

Resve A. Saleh, Masahiro Fukui, Tatsuya Koyagi, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Charge-borrowing decap: A novel circuit for removal of local supply noise violations

Resve A. Saleh, Steven J. E. Wilton, Xiongfei Meng, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Full-chip verification of UDSM designs

Resve A. Saleh, David Overhauser, Sandy Taylor, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling

Resve A. Saleh, Peter Hallschmid, 2007, 2007 44th ACM/IEEE Design Automation Conference.

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Testable and self-repairable structured logic design

Resve A. Saleh, Uthman Alsaiari, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Power Reduction of On-Chip Serial Links

Resve A. Saleh, Amit Kedia, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Active decap design considerations for optimal supply noise reduction

Resve A. Saleh, Xiongfei Meng, 2009, 2009 10th International Symposium on Quality Electronic Design.

Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations

Resve A. Saleh, J. G. Mueller, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip

Resve A. Saleh, Alireza Nasiri Avanaki, André Ivanov, 2007, Integr..

Generalized Power-Delay Metrics in Deep Submicron CMOS Designs

Resve A. Saleh, Dipanjan Sengupta, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analog IP design flow for SoC applications

Shahriar Mirabbasi, André Ivanov, Resve A. Saleh, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy

Resve A. Saleh, Uthman Alsaiari, R. Saleh, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2005, IEEE Transactions on Computers.

Methodologies and algorithms for testing switch-based NoC interconnects

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Trends in low power digital system-on-chip designs

Resve A. Saleh, G. Lim, T. Kadowaki, 2002, Proceedings International Symposium on Quality Electronic Design.

Effect of traffic localization on energy dissipation in NoC-based interconnect

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Improving the performance of parallel relaxation-based circuit simulators

Resve A. Saleh, Kyle A. Gallivan, Yen-Cheng Wen, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Essential Fault-Tolerance Metrics for NoC Infrastructures

Lorena Anghel, Partha Pratim Pande, Cristian Grecu, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Supply voltage selection in Voltage Island based SoC design

Resve A. Saleh, Dipanjan Sengupta, 2008, 2008 IEEE International SOC Conference.

RTL delay macro-modeling with Vt and Vdd variability

Resve A. Saleh, Masahiro Fukui, Sohaib Majzoub, 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks

Resve A. Saleh, Jeff Mueller, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Consistency checking and optimization of macromodels

Resve A. Saleh, Yun-Cheng Ju, Vasant B. Rao, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A scalable communication-centric SoC interconnect architecture

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Mixed-mode simulation and analog multilevel simulation

A. Richard Newton, Resve A. Saleh, Shyh-Jye Jou, 1994, The Kluwer international series in engineering and computer science.

A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS

Resve A. Saleh, Zahra Sadat Ebadi, R. Saleh, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

PVT variation impact on voltage island formation in MPSoC design

Rabab Kreidieh Ward, Resve A. Saleh, Sohaib Majzoub, 2009, 2009 10th International Symposium on Quality Electronic Design.

Exact evaluation of diagnostic test resolution

Resve A. Saleh, W. Kent Fuchs, Steven Parkes, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm

Rabab Kreidieh Ward, Resve A. Saleh, Steven J. E. Wilton, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Novel Active Decoupling Capacitor Design in 90nm CMOS

Resve A. Saleh, Karim Arabi, Xiongfei Meng, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers

Shahriar Mirabbasi, Resve A. Saleh, S. Shang, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Clock skew verification in the presence of IR-drop in the powerdistribution network

Resve A. Saleh, David Overhauser, Steffen Rochel, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits

Resve A. Saleh, Uthman Alsaiari, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2004, GLSVLSI '04.

Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs

Resve A. Saleh, Peter Hallschmid, R. Saleh, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On-line fault detection and location for NoC interconnects

Partha Pratim Pande, Cristian Grecu, André Ivanov, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Novel decoupling capacitor designs for sub-90nm CMOS technology

Resve A. Saleh, Karim Arabi, Xiongfei Meng, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm

Resve A. Saleh, Victor Aken Ova, R. Saleh, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Parallel event-driven waveform relaxation

Resve A. Saleh, Kyle A. Gallivan, Yen-Cheng Wen, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Incremental circuit simulation using waveform relaxation

Resve A. Saleh, Yun-Cheng Ju, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

System-on-Chip: Reuse and Integration

Shahriar Mirabbasi, Guy Lemieux, Alan J. Hu, 2006, Proceedings of the IEEE.

Dedicated autonomous scan-based testing (DAST) for embedded cores

André Ivanov, Resve A. Saleh, Mohsen Nahvi, 2002, Proceedings. International Test Conference.

iMACSIM: a program for multi-level analog circuit simulation

Resve A. Saleh, Jaidip Singh, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers

Resve A. Saleh, Zahra Sadat Ebadi, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A high-speed low-energy dynamic PLA using an input-isolation scheme

Shahriar Mirabbasi, Resve A. Saleh, Reza Molavi, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Multilevel and mixed-domain simulation of analog circuits and systems

Resve A. Saleh, Brian A. A. Antao, Jaidip Singh, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Resve A. Saleh, Imran Ashraf, Said Hamdioui, 2019, IEEE Access.